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Correcting method and corrector used for sampling time mismatch of time-interweaving ADC (analog to digital converter)

A technology of sampling time and time interleaving, applied in the field of microelectronics, can solve problems affecting the dynamic performance of analog-to-digital converters, and achieve the effects of guaranteed performance, improved performance, and low complexity

Active Publication Date: 2013-09-18
UNIV OF ELECTRONICS SCI & TECH OF CHINA
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AI Technical Summary

Problems solved by technology

However, in reality, there are non-ideal factors such as sampling time mismatch (Timing mismatch), gain mismatch (Gain mismatch), offset mismatch (Offset mismatch) and bandwidth mismatch (Bandwidth mismatch) among the sub-ADCs of each channel. , which seriously affects the dynamic performance of the entire ADC

Method used

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  • Correcting method and corrector used for sampling time mismatch of time-interweaving ADC (analog to digital converter)
  • Correcting method and corrector used for sampling time mismatch of time-interweaving ADC (analog to digital converter)
  • Correcting method and corrector used for sampling time mismatch of time-interweaving ADC (analog to digital converter)

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Embodiment

[0051] Taking the four-channel time-interleaved ADC as an example, such as Figure 4 As shown, its working principle is: the four clocks generated by the DLL are respectively sent to the sample and hold modules of the four channels, and the working time of the sample and hold modules of each channel is staggered. The channel ADC converts the output of the sample and hold module into a frequency f s / 8, N-bit digital codeword (wherein, f s interleaves the sampling frequency of the ADC for the entire time). The output of the channel ADC is sent to the multiplexer, and the multiplexer converts the output of each channel ADC into a frequency f s / 2 N-bit digital output.

[0052] When there is no sample time mismatch between channels, such as Figure 5 Shown by the solid line in the middle vertical line. make:

[0053] E 1 [ k ] ...

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Abstract

The invention relates to microelectronics, specifically to a time-interweaving ADC (analog to digital converter), in particular to a correcting method and a corrector used for sampling time mismatch of the time-interweaving ADC. The method mainly comprises the steps of performing subtraction on the digital outputs of adjacent channels of the time-interweaving ADC to solve a difference quantity Ei[k], representing the actual sampling time interval of adjacent channels with the average value Ai obtained after summing absolute values, representing the standard sampling time interval of adjacent channels, finally eliminating a statistic error of a relative error Bi by AAR filtering by obtaining the sampling time mismatch quantity of each channel, and feeding back to a clock generating unit to adjust a channel sampling clock after summing, thus realizing the negative feed back adjustment on the sampling time mismatch. The correcting method and the corrector used for the sampling time mismatch of the time-interweaving ADC have the beneficial effects of being capable of effectively improving and ensuring the performance of the multi-channel time-interweaving ADC and particularly suitable for high-speed low-power consumption analog to digital conversion, and having the advantages of low complexity, small hardware cost and easy implementation.

Description

technical field [0001] The present invention relates to microelectronic technology, in particular to a time-interleaved analog-to-digital converter (ADC), in particular to a correction method and a corrector for time-interleaved ADC sampling time mismatch. Background technique [0002] With the continuous improvement of integrated circuit manufacturing technology, high-speed, highly integrated digital circuits have been developed by leaps and bounds, and the digital signal processing capability has been continuously enhanced. In order to meet the demands of high-speed digital circuits, how to increase the speed of analog-to-digital converters has become the focus of attention of integrated circuit designers. [0003] An analog-to-digital conversion system that connects multiple analog-to-digital converters in parallel and uses interleaved clocks to make them work in turn has attracted widespread attention. Its characteristic is to improve the overall speed while maintaining...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03M1/10
Inventor 宁宁李靖李天柱胡勇王成碧眭志凌刘皓于奇
Owner UNIV OF ELECTRONICS SCI & TECH OF CHINA
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