Wafer-level packaging method and packaging structure thereof

A wafer-level packaging and wafer technology, which is applied in the manufacturing of electrical components, electrical solid-state devices, semiconductor/solid-state devices, etc., can solve the problems of low input and output port density, large package volume, poor reliability, etc. , The effect of small package size and thin package thickness

Inactive Publication Date: 2013-05-22
MEMSIC SEMICON WUXI
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] The technical problem to be solved by the present invention is to overcome the defects of low input and output port density, poor reliability, low production capacity, and large packaging volume existing in existing packaging products.

Method used

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  • Wafer-level packaging method and packaging structure thereof
  • Wafer-level packaging method and packaging structure thereof
  • Wafer-level packaging method and packaging structure thereof

Examples

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Embodiment Construction

[0030] Specific embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings.

[0031] In one embodiment of the wafer level packaging method involved in the present invention, it comprises the following steps:

[0032] First, a wafer 10 comprising chip units (not shown) is provided; see figure 1 , carry out bumping process (Bumping) and secondary passivation treatment on the front side of the wafer; where the bumping process can use known methods in the industry such as electroplating, sputtering or chemical replacement, and copper, nickel, antimony, gold or Bumps 11 of materials such as tin are grown on the front of the wafer; and the secondary passivation treatment generally involves growing a secondary passivation layer 16 on the front of the wafer, wherein the secondary passivation layer can be a polyimide film, etc. ;

[0033] Please refer to figure 2 A first groove 12 is opened between adjacent bumps 11 of adjac...

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PUM

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Abstract

The invention relates to a wafer-level packaging method and a packaging structure thereof. The packaging method comprises the following steps: providing a wafer which contains chip units; carrying out protrusion fabrication process on the front face of the wafer; forming a first groove between adjacent protrusions of the adjacent chip units on the front face of the wafer; filling coating materials in the first groove, wherein after the filling, the coating materials in the first groove are aligned with the surfaces of the chip units; forming a second groove in the back face of the wafer, wherein the depth of the second groove is equal to the difference between the thickness of the wafer and the thickness of the coating materials in the first groove; filling coating materials in the second groove, wherein after the filling, the height of the coating materials is higher than the back surface of the wafer; and carrying out simplified cutting. Through a wafer protrusion technology, wafer-level partial grooving and wafer-level coating material filling, high-density input / output ports of products and high reliability are achieved, the products are light, thin and short, productivity is high, and cost is low.

Description

technical field [0001] The invention relates to semiconductor packaging technology, in particular to a wafer-level packaging method and a packaging structure thereof. Background technique [0002] With the development of semiconductor technology, the functions of semiconductor chips are becoming more and more powerful, resulting in the continuous increase of the signal transmission volume of semiconductor chips, and the requirements for high-density input and output ports of chip units are getting higher and higher. On the other hand, the development of information technology tends to be thinner and smaller, which not only requires reducing the size of the chip package, but also requires ensuring the high reliability and stability of the chip unit. [0003] Whether it is BGA (abbreviation for Ball Grid Array, Ball Grid Array) package or QFN (abbreviation for Quad Flat Non-leaded, square flat non-leaded) package, the traditional chip-level packaging has gradually failed to me...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/56H01L23/31
CPCH01L2224/11H01L2924/10156
Inventor 李晓燕段志伟陈慧
Owner MEMSIC SEMICON WUXI
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