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Method for manufacturing lateral double-diffused metal oxide semiconductor (LDMOS) device

A technology of substrate and metal silicide layer, which is applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve the problems of LDMOS on-resistance Rdson increase, LDMOS performance degradation, and channel length lengthening, etc., to simplify Process complexity, Peeling elimination, high performance effect

Inactive Publication Date: 2013-02-13
CSMC TECH FAB1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

This will cause the length of the channel to become longer, and the on-resistance Rdson of the LDMOS will increase, which will degrade the performance of the LDMOS

Method used

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  • Method for manufacturing lateral double-diffused metal oxide semiconductor (LDMOS) device
  • Method for manufacturing lateral double-diffused metal oxide semiconductor (LDMOS) device
  • Method for manufacturing lateral double-diffused metal oxide semiconductor (LDMOS) device

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Experimental program
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Effect test

Embodiment 1

[0042] Such as figure 1 As shown, a method for manufacturing an LDMOS device provided by an embodiment of the present invention includes:

[0043] S101, providing a substrate.

[0044] refer to figure 2 , wherein the substrate 1 may be a silicon substrate. Of course, in other embodiments of the present invention, the substrate may also be a germanium substrate or a gallium arsenide substrate.

[0045] S102, sequentially forming a gate dielectric layer, a polysilicon layer, and a metal silicide layer on the substrate.

[0046] refer to image 3 , first forming a gate dielectric layer 2 on the substrate 1 . Wherein, the gate dielectric layer may be a silicon oxide layer. Those skilled in the art can understand that silicon oxide has a high dielectric strength (10 7 V / cm) and high resistivity (about 10 17 Ω·cm), so it is the preferred material for the gate dielectric layer. In practical applications, the thickness of the gate dielectric layer can be selected in a standa...

Embodiment 2

[0056] Such as Figure 7 As shown, another LDMOS device manufacturing method provided by the embodiment of the present invention includes:

[0057] S201, providing a substrate.

[0058] S202, sequentially forming a gate dielectric layer, a polysilicon layer and a metal silicide layer on the substrate.

[0059] S203, placing the substrate in a rapid heat treatment machine.

[0060] S204, heating the substrate in the rapid heat treatment machine to 1000°C.

[0061] S205, keeping the substrate in a rapid heat treatment machine for 1 min.

[0062] Of course, those skilled in the art can understand that other machines capable of performing rapid thermal annealing can also be used to perform rapid thermal annealing on the substrate. For devices with different technical requirements, the heating temperature and heating time for the rapid thermal annealing treatment of the substrate are different, which are not limited in the present invention.

[0063] S206 , etching the polysil...

Embodiment 3

[0066] Such as Figure 8 As shown, another LDMOS device manufacturing method provided by the embodiment of the present invention includes:

[0067] S301. Provide a substrate.

[0068] S302, sequentially forming a gate dielectric layer, a polysilicon layer and a metal silicide layer on the substrate.

[0069] S303, performing rapid thermal annealing treatment on the substrate.

[0070] S304. Spin-coat a photoresist layer on the metal silicide layer.

[0071] S305 , exposing the photoresist layer by means of a mask having a gate region pattern.

[0072] S306 , developing the exposed photoresist layer to form a photoresist layer with a gate region pattern.

[0073] S307 , using the photoresist layer with the gate region pattern as a mask to etch the polysilicon layer and the metal silicide layer to form a polysilicon plus metal silicide gate electrode.

[0074] S308, forming a channel region and a drift region in the substrate.

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Abstract

The invention discloses a method for manufacturing a lateral double-diffused metal oxide semiconductor (LDMOS) device. The method comprises the following steps of: providing a substrate; forming a gate dielectric layer, a polycrystalline silicon layer and a metal silicide layer on the substrate in sequence; performing rapid thermal annealing on the substrate; etching the polycrystalline silicon layer and the metal silicide layer to form a polycrystalline silicon and metal silicide gate electrode; and forming a channel region and a drift region in the substrate. By the method for manufacturing the LDMOS device, stress between the polycrystalline silicon layer and the metal silicide layer is relieved through rapid thermal annealing after the polycrystalline silicon layer and the metal silicide layer are formed, and the peeling phenomenon of metal silicide in the subsequent high temperature annealing process of forming the channel region and the drift region is avoided; and in addition, gradient impurity distribution of the channel region and self-aligned implantation of the drift region can be realized, so that the performance of the LDMOS device can be improved, and process complexity is reduced.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a method for manufacturing an LDMOS device. Background technique [0002] LDMOS (Lateral Double-diffuseMOS) devices are widely used in high-voltage radio frequency power circuits due to their advantages of high voltage resistance and low gate resistance. [0003] The manufacturing process of the traditional LDMOS device includes: the formation of the gate electrode of polysilicon plus metal silicide; the formation of the drift region and the channel region. Since the formation of the drift region and the channel region requires high-temperature furnace annealing treatment on the substrate, and the high-temperature furnace annealing process can easily cause warping or peeling of the metal silicide on the polysilicon gate. [0004] In order to avoid the Peeling phenomenon of metal silicide, an existing LDMOS device manufacturing process includes the following steps: (1) gro...

Claims

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Application Information

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IPC IPC(8): H01L21/336
Inventor 肖魁严以杰
Owner CSMC TECH FAB1
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