Semiconductor structure and manufacturing method thereof

Abstract

The invention provides a semiconductor structure and a manufacturing method thereof. The method comprises the steps of providing a semiconductor substrate, and forming a grid dielectric layer, a metal grid, a chemical-mechanical polishing (CMP) stop layer and a polycrystalline silicon layer sequentially on the semiconductor substrate; etching the grid dielectric layer, the metal grid, the CMP stop layer and the polycrystalline silicon layer to form a grid stack; forming a first interlayer dielectric layer on the semiconductor substrate to cover the grid stack and portions on two sides of the grid stack on the semiconductor substrate; and conducting planarization treatment to expose the CMP stop layer and enabling the CMP stop layer to be flush with the upper surface of the first interlayer dielectric layer. According to the semiconductor structure and the manufacturing method, the CMP stop layer is added, so that the height of the metal grid is effectively reduced, the capacitance of the metal grid and the capacitance of a contact area are effectively reduced, and a subsequent contact hole etching process is optimized.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a semiconductor structure and a manufacturing method thereof. Background technique [0002] With the development of the semiconductor industry, integrated circuits with higher performance and stronger functions require greater component density, and the size, size and space of each component, between components or each component itself need to be further reduced (currently, it can reach 45 nanometers or less), so the requirements for process control in the manufacturing process of semiconductor devices are relatively high. [0003] The height of the gate stack affects the parasitic capacitance between the gate and the source / drain (S / D) contact structure and its electrical extensions such as extension doping overlapping the gate and metallization contacts. The capacitance from the gate to the source / drain extension has a large impact on the overall speed of the integra...

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Problems solved by technology

Such thermal conditions are generally known to induce TED of the most pronounced host dopants, especially boron, causing detrimental effects on short-channel devices such as increased threshold voltage roll-off

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