Fabrication method of CMOS (complementary metal-oxide-semiconductor transistor) transistor

Abstract

The invention discloses a fabrication method of a CMOS (complementary metal-oxide-semiconductor transistor) transistor. The fabrication method comprises the steps of: providing a semiconductor structure, wherein the semiconductor structure comprises a semiconductor substrate, an NMOS (negative channel metal oxide semiconductor) transistor and a PMOS (positive channel metal oxide semiconductor) transistor formed on the semiconductor substrate; forming a strain layer on the surface of the NMOS transistor; etching the strain layer; exposing the PMOS transistor; carrying out a laser annealing process after carrying out primary peak annealing process; and carrying out secondary peak annealing process to restore damage generated by laser annealing, and removing the strain layer on the surface of the NMOS transistor. The damage generated by the semiconductor substrate is avoided, so that the performance and the yield of a semiconductor apparatus are improved.

Description

technical field [0001] The invention relates to the field of semiconductor device manufacturing, in particular to a manufacturing method of a CMOS transistor. Background technique [0002] With the rapid development of semiconductor manufacturing technology, the feature size (CD) of semiconductor devices has entered the sub-micron stage. In order to obtain faster computing speed, larger data storage capacity and more functions, semiconductor integrated circuits are constantly developing towards higher component density and high integration. [0003] Among them, complementary metal-oxide-semiconductor (CMOS) transistors, as basic units in modern logic circuits, include PMOS and NMOS. When the manufacturing process of CMOS transistors progresses to the micron level, since the channel between the source / drain regions becomes shorter, the short channel effect (Short Channel Effect) and the hot carrier effect (Hot Carrier Effect) will occur, and then cause the component to fail...

AI Technical Summary

Problems solved by technology

[0011] The existing CMOS device manufacturing process has the following problems: NMOS transistors are easy to apply the tensile stress of the surface stress layer to the bottom channel region through strain storage techniques such as laser annealing; during this process, the laser annealing makes the stress layer Deformation and extrusion of the semiconductor substrate, resulting in greater damage

However, before laser annealing, when ions are implanted into the semiconductor substrate to form the source / drain, the ions will cause damage and defects to the semiconductor substrate; the laser annealing temperature is very high, and these defects cannot be repaired, and after laser annealing, the silicon Defects in the crystal lattice can trap implanted atoms, causing an increase in the parasitic resistance between the source / drain, thereby degrading the performance of the semiconductor device

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