Linear voltage stabilizing circuit with low voltage difference

Abstract

The invention provides a linear voltage stabilizing circuit with low voltage difference. The linear voltage stabilizing circuit with the low voltage difference is provided with high power supply rejection ratio and comprises an error amplifier, a buffer circuit, a P-channel metal oxide semiconductor (PMOS) regulating transistor, a compensation circuit, a voltage division feedback circuit and an output circuit. The error amplifier is a novel error amplifier. Ratio of width to length ratio of a fifth PMOS tube and a sixth PMOS tube, ratio of width to length ratio of a seventh PMOS tube and an eighth PMOS tube and ratio of width to length ratio of a ninth N-channel metal oxide semiconductor (NMOS) tube and a tenth NMOS tube are all 1: K, and K is an integer greater than 1. The ratio of width to length ratio of the metal oxide semiconductor (MOS) tubes is changed, resistance of an output node of the error amplifier to a power supply is reduced, power interference enters from a current mirror low resistance point is amplified through current amplification technology, and power supply high frequency small signal interference in output signals of the error amplifier cannot be attenuated excessively. Therefore, the linear voltage stabilizing circuit with the low voltage difference enables power supply interference signals arriving at a PMOS regulating transistor grid to be varied according to variation of power supply voltage well, and improves the power supply rejection ratio of circuits.

Description

technical field [0001] The invention relates to the technical field of integrated circuits, in particular to a low-dropout linear regulator circuit. Background technique [0002] Low Dropout Regulator (LDO) is a step-down DC linear regulator. With the development of SOC technology, it is widely used in industries such as computers, communications, instrumentation, consumer electronics, and camera monitoring. . Although compared with the DC-DC switching voltage converter, the efficiency of the LDO is lower, but it has the advantages of fewer peripheral components, small ripple, low noise, small chip area, and simple circuit structure, so the LDO is used in power management chips. has always held a large proportion. [0003] With the improvement of integration, more and more LDOs are integrated into the SOC chip as a sub-module of the System on Chip (SOC) chip to supply power to a key module, and the powerful SOC chip integrates It is common to have multiple LDO modules pow...

AI Technical Summary

Problems solved by technology

[0008] In order to ensure the accuracy of the output voltage Vo and high PSRR at low frequency operation, the error amplifier OP is usually required to have a high gain, and the high gain leads to a large output node impedance of the error amplifier OP

This will result in a very low dominant pole of PSRR beyond which PSRR rolls off rapidly at 20dB / decade

[0009] In addition, in order to allow the LDO to have sufficient driving capability, the size of the PMOS adjustment transistor is generally large, and the large-size adjustment transistor itself will have a large parasitic capacitance (gate-to-drain capacitance C gd ), this parasitic capacitance is similar to the Miller capacitance, which will transmit high-frequency power supply interference to the output of the LDO, seriously deteriorating the high-frequency PSRR of the LDO circuit

[0010] In short, figure 1 The LDO circuit in the prior art shown has low power supply rejection ratio and poor ability to resist medium and high frequency power interference, so it cannot provide clean and reliable DC power for some high-speed and high-performance SOCs (such as pixel arrays in surveillance camera chips)

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