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Quad flat non-lead (QFN) package with leads arranged in plane array and manufacturing method

A leadless packaging, flat four-sided technology, used in semiconductor/solid-state device manufacturing, electrical components, electrical solid-state devices, etc., can solve the problems of shortening the life of the cutting blade, limiting the number of I/Os, reducing the cutting efficiency, etc. Surface mount quality, reduced packaging costs, and the effect of preventing metal burrs

Inactive Publication Date: 2012-02-15
BEIJING UNIV OF TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] With the improvement of IC integration and the continuous enhancement of functions, the number of I / Os of ICs increases, and the number of I / O pins of corresponding electronic packages also increases accordingly. The pins of the ring are arranged around the chip carrier, which limits the increase in the number of I / Os and cannot meet the needs of high-density ICs with more I / Os.
The traditional lead frame has no step structure design, which cannot effectively lock the plastic material, resulting in low bonding strength between the lead frame and the plastic packaging material, which is easy to cause delamination of the lead frame and the plastic packaging material or even the falling off of the pin or chip carrier, and cannot effectively Prevent moisture from diffusing into the electronic package along the interface between the lead frame and the plastic packaging material, which seriously affects the reliability of the package
Because the size of the traditional QFN product carrier is much larger than the size of the pins arranged around the periphery, when it is soldered on a circuit board such as a PCB, the large area of ​​solder under the chip carrier is likely to cause the drift of the package, resulting in the soldering of the pins arranged around the periphery. failure of
Traditional QFN products need to paste tape on the back of the lead frame in advance to prevent overflow during the plastic packaging process. After plastic packaging, cleaning processes such as removing the tape and molding compound flash need to be performed, which increases the packaging cost.
Use a dicing knife to cut and separate traditional quad flat no-lead packages. The dicing knife will also cut the lead frame metal while cutting the plastic packaging material, which will not only reduce the cutting efficiency and shorten the life of the dicing blade, but also produce metal burrs. , affecting the reliability of the package

Method used

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  • Quad flat non-lead (QFN) package with leads arranged in plane array and manufacturing method
  • Quad flat non-lead (QFN) package with leads arranged in plane array and manufacturing method
  • Quad flat non-lead (QFN) package with leads arranged in plane array and manufacturing method

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Experimental program
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Effect test

Embodiment Construction

[0062] The present invention is described in detail below in conjunction with accompanying drawing:

[0063] Figure 2A A schematic diagram of the rear surface of an area-array pin-arrangement QFN package structure in which the cross-section of the pins is circular and the pins are arranged in parallel according to the embodiment of the present invention. Figure 2B A schematic diagram of the rear surface of an area array pin arrangement QFN package structure in which the cross section of the pins is rectangular and the pins are arranged in parallel according to the embodiment of the present invention.

[0064] refer to the above Figure 2A -B It can be seen that, in this embodiment, the QFN package structures 200a and 200b with area array pin arrangement have pins 201 arranged in an area array distribution, and the arrangement of the pins 201 is parallel arrangement, under the pins 201 A metal material layer 23 is arranged on the surface, and an insulating filling material ...

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PUM

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Abstract

The invention discloses a quad flat non-lead (QFN) package with leads arranged in a plane array and a manufacturing method. The package comprises a chip carrier, leads, metal material layers, an IC chip, insulating filling materials, bonding materials, metal conductors and plastic package materials, wherein the chip carrier has a groove structure and leads for grounding; the plurality of leads are distributed in a plane array mode in a package structure; the metal material layers are arranged on the upper surfaces and lower surfaces of the chip carrier and the leads; the IC chip is arranged on a metal material layer on the upper surface of the chip carrier or on metal materials layers on the upper surfaces of the leads; the insulating filling materials are arranged below stepped structures of the leads and in grooves of the chip carrier; the bonding materials are arranged between the IC chip and the metal material layer on the upper surface of the chip carrier or between the IC chip and the metal material layers on the upper surfaces of the leads; and the plastic package materials are used for wrapping and sealing to form the package body. The package and the manufacturing method have the following beneficial effects: the bottleneck of low I / O quantity is broken through and the package reliability is improved.

Description

technical field [0001] The invention relates to the technical field of manufacturing semiconductor components, in particular to a quadrilateral flat no-lead package with area array pin arrangement, and the invention also includes a manufacturing method of the package. Background technique [0002] With the development of electronic products such as mobile phones and notebook computers towards miniaturization, portability, ultra-thinness, multimedia and low-cost requirements for popularization, high-density, high-performance, high-reliability and low-cost packaging forms and Its assembly technology has been developed rapidly. Compared with the expensive BGA and other packaging forms, the new packaging technology developed rapidly in recent years, that is, the quad flat non-lead QFN (Quad Flat Non-lead Package) package, due to its good thermal performance and electrical performance, small size, Many advantages such as low cost and high productivity have triggered a new revolu...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L23/49H01L23/31H01L21/48H01L21/56
CPCH01L24/97H01L2224/48247H01L2224/92H01L2224/92247H01L2224/97H01L2924/01082H01L2924/14H01L2924/181H01L2924/30107H01L2924/3011H01L2224/83H01L2224/85H01L2924/00H01L2924/00012
Inventor 秦飞夏国峰安彤武伟刘程艳朱文辉
Owner BEIJING UNIV OF TECH
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