Cell Structure of Dual Port Static Random Access Memory

Abstract

The present disclosure provides a dual port static random access memory (SRAM) cell. The dual-port SRAM cell includes a first and second inverters cross-coupled for data storage, each inverter includes a pull-up device (PU) and a plurality of pull-down devices (PDs); a plurality of pass gate devices configured with the two cross-coupled inverters; and at least two ports coupled with the plurality of pass gate devices (PGs) for reading and writing, wherein each of PU, PDs and PGs includes a fin field-effect transistor (FinFET), a ratio between a number of PDs in the SRAM cell and a number of PGs in the SRAM cell is greater than 1, and a number of FinFETs in the SRAM cell is equal to or greater than 12.

Description

technical field [0001] The present disclosure relates to the cell structure of static random access memory (SRAM), especially dual-port SRAM. Background technique [0002] In deep sub-micron integrated circuit technology, embedded static random access memory (SRAM) devices are commonly used in high-speed communication, image processing and system-on-chip (SOC) products. storage unit. For example, a dual port (DP) SRAM device allows parallel operations, such as 1R (read) 1W (write) or 2R (read) in one cycle, and thus has a higher bandwidth than a single-port SRAM. In the advanced technology of shrinking feature size and increasing packing density, low load and high speed of cell structure are important factors for embedded memory and system-on-chip products. Thin SRAM cell structure with short bit line (BL) provides better performance on bit line RC delay. Nevertheless, the thin cell structure suffers from several problems including data node leakage, pull-down (PD) / pass-g...

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Problems solved by technology

This results in an L-shaped or T-shaped layout of the drain terminal of the pull-down device, and thus may suffer from the above-mentioned problems

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