Manufacturing method of VC SOI nLDMOS (Vertical Channel Silicon-on-insulator n Lateral Double-diffused Metal Oxide Semiconductor) device unit with p-type buried layer

A manufacturing method and device technology, applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve problems that are not conducive to improving device and system reliability, saving energy and protecting the environment, affecting device voltage withstand performance, and device working efficiency. Low problems, to achieve the effect of improving work efficiency and thermal stability, improving electrical and thermal properties, and protecting the environment

Inactive Publication Date: 2011-08-17
HANGZHOU DIANZI UNIV
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  • Description
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Problems solved by technology

[0013] When a high voltage is applied to the drain of the vertical channel SOI NLDMOS device fabricated by this method, since the substrate under the buried insulating layer hardly participates in the withstand voltage, the withstand voltage performance of the device is seriously affected, and the thick buried oxide layer affects the device. The heat dissipation of the device is low, and the device is easy to generate heat, which is not conducive to improving the reliability of the device and system, saving energy and protecting the environment

Method used

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Embodiment Construction

[0028] A method for manufacturing a vertical channel SOI nLDMOS device unit with a p-buried layer, specifically comprising the following steps:

[0029] 1. Select a polished SOI wafer with a thick p-type buried layer (BPL) as the initial material. The SOI wafer includes a p-type semiconductor substrate, a thin buried insulating layer, and a p-type buried layer from bottom to top. The p-type semiconductor substrate and the p-type buried layer region are completely isolated by a thin buried insulating layer, and the thin one is the n-type top layer silicon covering the p-type buried layer region for making devices and circuit;

[0030] 2. Perform the first oxidation on the upper surface of the exposed top silicon film, the thickness of the oxide layer is 100-300nm, and then use the designed buffer doping mask to perform the first photolithography on the exposed oxide layer to remove The exposed oxide layer forms a buffer doping window, and n-type impurities are doped in the buf...

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Abstract

The invention relates to a manufacturing method of a VC SOI nLDMOS (Vertical Channel Silicon-on-insulator n Lateral Double-diffused Metal Oxide Semiconductor) device unit with a p-type buried layer. The SOI nLDMOS device manufactured by the prior art seriously limits vertical voltage resistance and lateral voltage resistance, and has serious self-heating effect and poor high temperature resistance and thermal stability. Through the manufacturing method disclosed by the invention, ten times of photoetching are carried out on an SOI thick film material with the p-type buried layer to manufacture the VC SOI nLDMOS device with the p-type buried layer, and a formed depletion layer bears the vast majority of vertical withstand voltage when the VC SOI nLDMOS device applies a high voltage between a drain electrode and a source electrode in the blocking state, thus the vertical voltage resistance of the VC SOI nLDMOS device is improved, the self-heating effect of the device is remarkably reduced, and the high temperature resistance and the thermal stability are improved; furthermore, the volume and the weight of a system are reduced, the resource is saved, the energy consumption is reduced and the environment is protected.

Description

technical field [0001] The invention belongs to the technical field of microelectronics, and relates to a device unit of a vertical channel (VC) SOI (semiconductor on insulating layer) nLDMOS (n-type lateral double-implanted metal-oxide-semiconductor field-effect transistor) with a p-type buried layer Integrated fabrication methods for SOI (Semiconductor On Insulator) CMOS (Complementary Metal-Oxide-Semiconductor) VLSI (Very Large Scale Integration) processes. Background technique [0002] Vertical channel (VC) SOI nLDMOS devices are used as Non-contact power electronic switches, power drivers or RF power amplifier transistors have great potential in technical fields such as intelligent power electronics, high-temperature environment power electronics, space power electronics, vehicle power electronics, communications, remote sensing, aerospace, military defense, and the Internet of Things. widely used. SOI CMOS VLSI process technology has advantages such as high process m...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/762H01L21/336
Inventor 张海鹏许生根吴倩倩孔令军汪洋赵伟立刘怡新
Owner HANGZHOU DIANZI UNIV
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