Phase locked loop with zero phase error

Abstract

The invention belongs to the field of semiconductor integrated circuit design, in particular relating to a phase locked loop with zero phase error. The phase locked loop comprises a phase and frequency discriminator (PFD), a charge pump (CP), a loop filter (LPF), a voltage-controlled oscillator (VCO) and a frequency divider, and is characterized in that PFD comprises four input ports, and the input signals of the four input ports are respectively an external reference resource (fref), an oscillation signal (fvco) output by the VCO, the fref_1 obtained through the M times frequency demultiplication of the fref by another frequency divider, and a feedback signal (f1) obtained through the N times frequency demultiplication of the fvco by the frequency divider. The phase locked loop with zerophase error realizes the functions of the frequency discrimination of the fref_1 and the f1, and the phase discrimination of the fref and the fvco, so that the problem of unpredictable time delay existing between the output signal and the input signal of the VCO is solved, the appearing of the timing sequence problem in the application is avoided, and the operating speed and the reliability of the chip are effectively ensured.

Description

technical field [0001] The invention belongs to the field of semiconductor integrated circuit design, and in particular relates to a phase-locked loop. The phase-locked loop includes a frequency and phase detector capable of locking the frequency and phase of a specified signal. Background technique [0002] With the rapid development of integrated circuit technology, the number of transistors integrated on a single silicon crystal is increasing, and the working speed of the chip is also increasing. Compared with past low-speed low-integration chips, the clock requirements are more stringent. Whether it is off-chip or on-chip, it is required that the frequency stability of the clock signal is high and the jitter is small, and the phase shift of the clock signal between modules is small enough. However, due to the existence of parasitic effects, such a high-frequency high-speed clock signal cannot be directly input into the chip from the outside. It can only be realized by ...

AI Technical Summary

Problems solved by technology

[0005] The technical problem to be solved by the present invention is to overcome the defects in the prior art and solve the problem that the phase-locked loop cannot lock the phase between the VCO output and the input reference signal after locking the frequency

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