Method for manufacturing n-metal-oxide-semiconductor (NMOS) transistor

Abstract

The invention discloses a method for preparing an n-metal-oxide-semiconductor (NMOS) transistor, comprising the following steps: doping n-type ions in a provided semiconductor substrate with a grid structure at the two sides of the grid structure to form a source light dope region and a drain light dope region; forming lateral wall spacers at the two sides of the grid structure; doping antimony ions and carbon ions in the semiconductor substrate at the two sides of the grid structure with the lateral wall spacers; and doping n-type ions in the semiconductor substrate at the two sides of the grid structure with the lateral wall spacers to form a source heavy dope region and a drain heavy dope region, thus improving the performance of a semiconductor device.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a manufacturing method of an NMOS transistor. Background technique [0002] With the rapid development of semiconductor manufacturing technology, in order to achieve faster computing speed, larger data storage capacity and more functions of semiconductor devices, semiconductor wafers are developing towards high integration, and the gate feature size of MOS devices has entered deep In the sub-micron stage, the conductive channel under the gate becomes thinner and shorter than before, so the requirements for the process are getting higher and higher. [0003] In conventional semiconductor manufacturing techniques, NMOS transistors are formed, Figure 1 to Figure 3 For a schematic diagram of forming an NMOS transistor using conventional methods, refer to Figure 1 to Figure 3 First, a semiconductor substrate 10 is provided, and a p-well 20 is formed in the semico...

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Problems solved by technology

[0006] However, as the size of the device decreases, the depth and concentration of ion implantation become more and more difficult to control, so that the resistance and junction depth of the source and drain regions of the NMOS transistor obtained by the above-mentioned traditional method cannot meet the requirements, thus making The performance of semiconductor devices deteriorates

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