Double-fin type channel double-grid multifunction field effect transistor and producing method thereof

Abstract

This invention provides a double-fin channel double-grid multifunction field effect transistor and its preparation method, in which, the field effect transistor has a silicon substrate, the channel is two same fins with rectangular sections to form a double-fin channel, the outside of each is oxygen grid and front grid, the inside of which is tunnel through oxidation layer, a SiN4 trap layer, a block oxidation layer and a back grid to form a double-grid structure, two ends of the double-fin channel is connected with a common n+source and n+drain, the front and back grids are aligned covering little part of the n+source and n+drain, a thick SiO2 insulation layer is set just under the channel and the silicon substrate connected with the n+source and the n+drain to form a structure with the double-fin channel on the insulation layer.

Description

technical field [0001] The invention belongs to the technical field of metal oxide semiconductor field effect transistor (MetalOxide Semiconductor Field Effect Transistor-MOSFET) in ultra-large-scale integrated circuit (ULSI), in particular to a double-fin-type channel double-gate multifunctional field-effect transistor and its preparation method. Background technique [0002] With the wide application and high-speed development of VLSI, based on MOSFET, System On Chip (SOC) technology has aroused people's great interest more and more. The system chip is to integrate the whole system on one or as few integrated circuit chips as possible, and each chip can integrate two or more functions from the original single function. SOC technology can overcome various problems in board-level integration of multi-chips (such as delay between chips, reliability of printed circuit boards), and has outstanding advantages in improving system performance, reducing power consumption, and easy...

AI Technical Summary

Problems solved by technology

[0006] However, the SOONO structure MOSFET multifunctional device shown in Document 1 is based on a planar double-gate device, and has the following problems: (1) The back gate ONO stack structure is too thick due to the device structure and manufacturing process (respectively 1.4nm, 42nm, 1.4nm, the total thickness reaches about 45nm), which makes the threshold window small (2.5V), the back gate voltage during programming / erasing is higher (up to 6V / -4V), and the programming / erasing time is longer (up to 0.5 ms / 0.5ms), the application of a thin tunnel oxide layer (1.4nm) makes the retention characteristics worse, and the too thick silicon nitride trap layer makes the redistribution of injected charges affect the reliability of the device; (2) compared with conventional MOSFETs The preparation method needs to add two layouts: a Stripe version (remove the SiGe sacrificial layer), a deep trench isolation layout, used to isolate different back gates; (3) the back gate completely covers the channel and source and drain, in Band-band tunneling hot holes during erasing will be injected into the coverage area of ​​the back gate and drain, affecting the DC characteristics and reliability of the device

(4) The SiGe layer as the sacrificial layer and the silicon layer as the channel are both epitaxially grown, and the process cost is relatively high

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