Film stress detecting method

A stress detection and film layer technology, applied in the field of integrated circuit manufacturing, can solve the problem of difficulty in achieving accurate thickness measurement in the selected area of ​​the sample, and achieve the effects of reducing waste chip loss, expanding the process range and reducing production costs.

Inactive Publication Date: 2009-03-11
SEMICON MFG INT (SHANGHAI) CORP +1
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  • Abstract
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  • Claims
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Problems solved by technology

Obviously, although applying this inventive method can carry out stress detection to any position in the film, and can guarantee that this test has high sensitivity, but the sensitivity of the stress value measured depends on the thickness of the sample selected area, and for the sample selected area Accurate measurement of thickness is not easy to achieve in production

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  • Film stress detecting method
  • Film stress detecting method

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no. 2 example

[0051] As a second embodiment of the present invention, the specific steps of applying the method of the present invention to detect film stress include:

[0052] First, film deposition-photolithography-etching steps are performed on a semiconductor substrate to obtain a patterned film layer.

[0053] The semiconductor substrate includes a graphic area and a non-graphical area, the graphic area is used to make device products, and the non-graphical area is used to undertake various marks needed in the actual production process, such as alignment marks and measurement Marking, etc., and provide cutting channels after the device is completed. Alignment marks are included in the non-pattern area of ​​the semiconductor substrate. The alignment mark is used to provide an alignment point located in the non-pattern area of ​​the semiconductor substrate required for an alignment operation by using the exposure device to form a patterned film layer. As a second embodiment of the pres...

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Abstract

A film layer stress detection method comprises the following steps that: a patterned film layer is formed on a semiconductor substrate which comprises an alignment mark; the patterned film layer comprises a counterpoint mark or a measuring mark; with the alignment mark, the counterpoint mark and / or the measuring mark, the counterpoint operating deviation information of the corresponding areas of different counterpoint mark and / or measuring mark in the film layer is achieved; a counterpoint operating deviation standard of the film layer is determined; according to the counterpoint operating deviation standard of the film layer, the counterpoint operating deviation information of the corresponding areas of different counterpoint mark and / or measuring mark in the film layer is distinguished. With the method, the film layer stress can achieve online detection without adding separate detection procedures; the overproof stress information of different areas of the film layer can be provided; the waste chip loss and the production cost are reduced; the testing result has no relation with other parameters of the film layer.

Description

technical field [0001] The invention relates to the technical field of integrated circuit manufacturing, in particular to a film layer stress detection method. Background technique [0002] In order to meet the needs of device miniaturization development, integrated circuit manufacturing technology usually adopts multi-layer thin film structure. Typically, thin films with a multilayer structure generate internal film stress due to lattice mismatch within or between layers. In addition, the properties of different materials such as elasticity, thermal expansion, etc. will also lead to the generation of internal membrane stress. Excessive film stress often leads to serious degradation of film material properties, and even causes device failure in severe cases. For example, for dynamic random access memory (DRAM) chips, lattice dislocation caused by excessive film stress may cause electrical signal Keep changing over time. Therefore, in the actual production process, the mem...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/66
Inventor 何伟明林益世
Owner SEMICON MFG INT (SHANGHAI) CORP
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