Eureka AIR delivers breakthrough ideas for toughest innovation challenges, trusted by R&D personnel around the world.

Method for reducing feature size and semi-conductor etching method

A feature size, semiconductor technology, applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve problems such as linear distortion, unstable photoresist, insufficient thickness of photoresist layer, etc., to achieve accurate effect of size

Active Publication Date: 2009-01-14
UNITED MICROELECTRONICS CORP
View PDF5 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] However, the process of trimming the photoresist is not stable, and it is easy to cause insufficient thickness of the remaining photoresist layer due to too fast etching, and cause necking or widening phenomenon, and photoresist The uneven shape of the etchant makes the sidewall of the gate rough or linearly distorted, which affects the shape of the formed gate and the consistency of the feature size

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Method for reducing feature size and semi-conductor etching method
  • Method for reducing feature size and semi-conductor etching method
  • Method for reducing feature size and semi-conductor etching method

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0036] Figure 2A to Figure 2B Shown is a cross-sectional view of the fabrication process of a method for reducing feature size according to a preferred embodiment of the present invention. Please refer to Figure 2A Firstly, a dielectric layer 202 is formed on a substrate 200 . Wherein, the material of the dielectric layer is, for example, silicon oxide, silicon nitride or silicon oxynitride. A patterned photoresist layer 204 is then formed on the dielectric layer 202 to expose part of the dielectric layer 202 . Wherein, the patterned photoresist layer 204 has a first line width L1.

[0037] Next, please refer to Figure 2B , using the patterned photoresist layer 204 as an etching mask, an etching process is performed under an environment with a pressure of, for example, 80-400 Torr and a temperature of, for example, -50° C. to 50° C. to remove the exposed dielectric layer 202 and make the final line width L2 of the reduced patterned photoresist layer 204' and the patter...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

This invention relates to one method to contract characteristic sizes, which comprises the following steps: forming medium layer onto under layer; then forming pattern light anti-erosion layer on medium layer to expose part medium layer with first line width; then using pattern light anti-erosion layer as etching mask for etching to remove exposed medium layer with final width less than first line width.

Description

technical field [0001] The present invention relates to a semiconductor process, in particular to a method for shrinking a critical dimension (CD) and a semiconductor etching method. Background technique [0002] Metal-oxide semiconductor (MOS) transistors are very important electronic components in integrated circuits. Therefore, the electrical performance of metal-oxide semiconductor transistors will affect the quality of products. A general method to improve the electrical performance of metal-oxide-semiconductor transistors is to reduce the minimum line width (line width) of the gate to increase the working speed of the gate. Usually, when making the gate, it is necessary to form a hard mask layer on the polysilicon layer first, and then use a layer of patterned photoresist on the hard mask layer as an etching mask, and then process the hard mask layer Etching, and finally etching the polysilicon layer using the hard mask layer as a mask to form a gate. However, this m...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/311
Inventor 蔡彰祜
Owner UNITED MICROELECTRONICS CORP
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Eureka Blog
Learn More
PatSnap group products