Dual-node capacitor coupled MOSFET for improving ESD performance

Abstract

A dual-node capacitor coupling technique is used to lower the trigger voltage and to improve the uniform turn-on of a multi-finger MOSFET transistor. Preferably, each MOSFET is an NMOS device. Specifically, each NMOS device includes a capacitor that is connected between the gate of the NMOS device and the pad terminal. A first resistor is connected between the gate and the p-well, while a second resistor is connected between the p-well and the grounded source. For a positive ESD pulse to VSS, the p-well is pulled up to approximately 0.7 V during the initial ESD event, such that the source junction is forward biased and that the trigger voltage of the NMOS device is lowered. At the same time the gate voltage is coupled within the range of approximately 1 to 2 V to promote the uniform turn on of the gate fingers of the NMOS devices during the initial ESD event.

Description

FIELD OF THE INVENTIONThe present invention relates to a primary ESD protection circuit, and more particularly, the present invention relates to a primary ESD protection circuit having a dual-node capacitor coupled multi-finger NMOSFET structure.BACKGROUND OF THE INVENTIONElectrostatic discharges (ESDs) from human handling of a metal-oxide semiconductor (MOS) IC chip, or from other causes, permanently damage the IC chip. Often the thin-oxide layer that isolates the gate electrode from the substrate of a MOS field effect transistor is irreparably ruptured by a voltage spike applied across it. A voltage spike or ESD is often applied to the gate, because the gate electrode is connected to an external terminal or pin of the IC chip. The external terminals are formed on an input or output pad. To prevent such damage from excessive electrostatic discharges, a protective device is often connected between the pad and the internal circuits.As CMOS technology is scaled down into submicron reg...

AI Technical Summary

Benefits of technology

The present invention overcomes the deficiencies of the prior art. Specifically, a dual-node capacitor coupling technique is used to lower the trigger voltage and to improve the uniform turn-on of a multi-finger MOSFET transistor.

Problems solved by technology

Electrostatic discharges (ESDs) from human handling of a metal-oxide semiconductor (MOS) IC chip, or from other causes, permanently damage the IC chip.

Often the thin-oxide layer that isolates the gate electrode from the substrate of a MOS field effect transistor is irreparably ruptured by a voltage spike applied across it.

Submicron CMOS devices, such as short channel thin-oxide MOS devices, are extremely susceptible to ESD damage.

This occurs when a strong electric field across the depletion region in the drain substrate junction becomes high enough to begin avalanche breakdown, which in turn causes impact ionization, resulting in the generation of both minority and majority carriers.

For manufacturing purposes, however, layout area is typically at a premium, and a conventional long-finger structure may not fit in the designated layout area.

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