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Flux-free chip to wafer joint serial thermal processor arrangement

a thermal processor and chip technology, applied in the field of electronic chips, can solve the problems of reducing the reliability of the device produced, the inability to perfectly clean the die and the wafer, and the removal of flux, so as to reduce the surface oxides of lead, tin, copper and silver. the effect of reducing the voids

Inactive Publication Date: 2012-08-28
SEMLGEAR INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

"The present invention relates to a method of manufacturing solder bumps and solder joints on a semiconductor material. The method involves using a treatment system that includes a rotary production table with multiple treatment positions. The process involves heating the materials to be joined, such as a pre-soldered semiconductor wafer and a pre-attached chip or die, and then transferring them to a vacuum chamber for further removal of trapped air, moisture, and reaction by-products. The materials are then returned to room temperature and pressure, and the process is repeated for subsequent stations until the final melt-joining of the solder ball to the solder pad is complete. The invention provides a method that allows for individual control of the processing temperatures at each station and ensures efficient removal of trapped air, moisture, and reaction by-products."

Problems solved by technology

Removal of that flux is one of the problems common to the prior art.
The flux in between the die and the wafer is impossible to perfectly clean, thereby reducing the reliability of the device produced.
Due to the nature of fluxes utilized in the prior art, they adhere to the processing equipment and make that equipment very difficult to be cleaned.
The use of fluxes requires a lot of chemical consumption and a lot of maintenance for the manufacturing process.
By using a vacuum system for solder reflow, there are several disadvantages, such as the lack of heat transfer media.

Method used

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  • Flux-free chip to wafer joint serial thermal processor arrangement
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  • Flux-free chip to wafer joint serial thermal processor arrangement

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Embodiment Construction

[0047]The invention a an electronic chip and chip manufacturing process which comprises a rotatable, circumferentially organized, serial thermal processing station arrangement 10 using a method for serially treating a pre-assembled chip or die and a wafer assembly “W” through a series of preferably at least six independent, enclosed station chambers in the processor arrangement 10, as represented in FIG. 1.

[0048]The rotary production station arrangement 10 is arranged to rotate so as to present a material to be treated, such as a semiconductor wafer, at a series of circumferentially spaced-apart locations, from a Load / Lock station to processing stations numbered 1 through 5, which stations each are arranged to independently control the temperature, pressure and atmosphere thereat, as is similarly represented in various aspects and embodiments of the arrangement 10, in a mechanism as may be shown in the above-identified '789 and '879 patents, incorporated by reference herein.

[0049]Th...

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Abstract

A serial thermal processing arrangement for treating a pre-assembled chip / wafer assembly of semiconductor material in a rotary processor, through a series of intermittent, rotatively advanced, movements into independent, temperature and pressure controlled, circumferentially disposed chambers.

Description

BACKGROUND OF THE INVENTIONField of the Invention[0001]The present invention relates to an electronic chip and to a method of manufacturing same such as semiconductor wafers and more particularly to a stepwise process of a machine utilized in that manufacture of semiconductor wafers and is a continuation-in-part application of co-pending U.S. patent application Ser. No. 12 / 930,462 (Semigear-22) filed concurrently herewith, and wherein the present application claims the benefit of and is a CIP of Ser. No. 12 / 653,454, filed Dec. 14, 2009 now U.S. Pat. No. 7,982,320, which is a division of Ser. No. 11 / 482,838, filed Jul. 7, 2006, now U.S. Pat. No. 7,632,750, which is a CIP of Ser. No. 10 / 832,782, filed Apr. 27, 2004, now U.S. Pat. No. 7,008,879, which is a division of Ser. No. 10 / 186,823, filed Jul. 1, 2002, now U.S. Pat. No. 6,827,789, each incorporated herein by reference in the present Application.DESCRIPTION OF THE PRIOR ART[0002]Formation of a solder bump on a semiconductor substr...

Claims

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Application Information

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Patent Type & Authority Patents(United States)
IPC IPC(8): H01L21/44
CPCB23K3/0623H01L24/11H01L24/742H01L24/75H01L24/81H01L24/83H01L24/92H01L21/68764H01L21/68771B23K2201/40H01L2224/16H01L2924/01027H01L2924/01029H01L2924/01047H01L2924/01074H01L2924/01075H01L2924/01078H01L2924/01082H01L2924/14H01L2924/01006H01L2924/01023H01L2924/01322H01L2924/014H01L2224/83948H01L2224/75102H01L2224/755H01L2224/81948H01L2224/758H01L2224/131H01L2224/291H01L2224/73203H01L2224/7565H01L2224/81065H01L2224/81193H01L2224/8121H01L2224/81815H01L2224/81986H01L2224/83065H01L2224/8309H01L2224/83193H01L2224/8321H01L2224/83815H01L2224/83986H01L2224/9205H01L2224/92125H01L2224/8109H01L2224/7501H01L21/67098H01L2224/1131H01L2224/10135H01L2224/10165H01L2924/00013H01L2224/81141H01L2224/11334H01L2224/13099H01L2224/13599H01L2224/05599H01L2224/05099H01L2224/29099H01L2224/29599B23K2101/40H01L2224/81205
Inventor ZHANG, JIAN
Owner SEMLGEAR INC
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