System to enable a memory hub device to manage thermal conditions at a memory device level transparent to a memory controller

Abstract

A memory system is provided that manages thermal conditions at a memory device level transparent to a memory controller. The memory systems comprises a memory hub device integrated in a memory module, a set of memory devices coupled to the memory hub device, and a first set of thermal sensors integrated in the set of memory devices. A thermal management control unit integrated in the memory hub device monitors a temperature of the set of memory devices sensed by the first set of thermal sensors. The memory hub device reduces a memory access rate to the set of memory devices in response to a predetermined thermal threshold being exceeded thereby reducing power used by the set of memory devices which in turn decreases the temperature of the set of memory devices.

Description

GOVERNMENT RIGHTS[0001]This invention was made with United States Government support under Agreement No. HR0011-07-9-0002 awarded by DARPA. THE GOVERNMENT HAS CERTAIN RIGHTS IN THE INVENTION.BACKGROUND[0002]1. Technical Field[0003]The present application relates generally to an improved data processing system and method. More specifically, the present application is directed to enabling a memory hub device to manage thermal conditions at a memory device level transparent to a memory controller.[0004]2. Description of Related Art[0005]Contemporary high performance computing main memory systems are generally composed of one or more dynamic random access memory (DRAM) devices, which are connected to one or more processors via one or more memory control elements. Overall computer system performance is affected by each of the key elements of the computer structure, including the performance / structure of the processor(s), any memory cache(s), the input / output (I / O) subsystem(s), the effic...

AI Technical Summary

Benefits of technology

[0010]In order to increase the available bandwidth of a memory channel, the illustrative embodiments break the link between the operating frequency of the memory channel and the operating frequency of the memory devices. Typically, the operating frequency of the memory channel is directly linked to some multiple of the operating frequency of the memory devices. At a system level the maximum bandwidth and lowest latency will be when the memory devices are running at the maximum frequency of the memory controller. While the memory channel is capable of operating at other frequencies, any frequency that is lower then the maximum design point of the memory controller will result in lower bandwidth, higher latency and therefore lower performance. In a general computer system, there may be a number of design tradeoffs that will result in a lower operating frequency in the memory subsystem. These design tradeoffs include, but are not limited to, electrical loading due to memory capacity on the memory channels, power reduction in the memory devices that may result in operating the memory devices at a operating frequency lower then the maximum design point, and cost tradeoff's that result in a lower frequency at the memory device interface. By lowering the operating frequency of the memory devices, the operating frequency of the memory channel may also be reduced and, thus, the bandwidth of the memory channel decreases and the latency to access data from memory devices increases.

[0011]The illustrative embodiments provide mechanisms for enabling a memory hub device to manage thermal conditions at a memory device level transparent to a memory controller. By breaking the link between operating frequency of the memory channel and the operating frequency of the memory devices, the memory hub device may use a thermal management control unit to manage thermal conditions within the memory devices and / or the memory hub device itself transparent from operations of memory controller. Thus, when the temperature within a memory device and / or the memory hub device rises past a predetermined temperature limit, the memory hub device may reduce the memory access rate to the memory device or all memory devices to reduce the power being used by the memory devices. By reducing the memory access rate to the memory devices, the current drawn by memory devices decreases and the temperature within the memory devices will decrease.

[0013]In the illustrative embodiments, a thermal management control unit integrated in the memory hub device may monitor a temperature of the set of memory devices sensed by the first set of thermal sensors. In the illustrative embodiments, the memory hub device may reduce a memory access rate to the set of memory devices in response to a predetermined thermal threshold being exceeded thereby reducing power used by the set of memory devices which in turn decreases the temperature of the set of memory devices.

[0014]The illustrative embodiments may further comprise a second set of thermal sensors integrated in the memory hub device. In the illustrative embodiments, the memory hub device may monitor the temperature of the memory hub device sensed by the second set of thermal sensors. In the illustrative embodiments, the memory hub device may reduce a memory access rate to the set of memory devices in response to the predetermined thermal threshold being exceeded thereby reducing power used by the set of memory devices which in turn decreases the temperature of the memory hub device.

Problems solved by technology

High-availability systems, i.e. systems that must be available to users without failure for large periods of time, present further challenges related to overall system reliability due to customer expectations that new computer systems will markedly surpass existing systems with regard to mean-time-before-failure (MTBF), in addition to offering additional functions, increased performance, increased storage, lower operating costs, etc.

Other frequent customer requirements further exacerbate the memory system design challenges, and include such items as ease of upgrade and reduced system environmental impact, such as space, power, and cooling.

Further, the capacity of the memory subsystem is limited by the number of memory devices that can be attached to a memory channel and still run within the power constraints of the memory subsystem.

The link between the operating frequency of the memory channel and the operating frequency of the memory devices makes it difficult to optimize the capacity, bandwidth, and power for the memory subsystem.

For example, as DRAM devices are added to a DIMM to increase the capacity of the DIMM, the additional electrical loading that results from the addition of the DRAM chips will result in a lower frequency of operation of the DRAM interface.

With the fixed ratio between the DRAM clock rate and the memory channel rate, this reduction in DRAM frequency results in a direct loss of bandwidth and system performance.

Thus, the memory channel frequency link to the frequency of the memory devices presents a limiting factor for optimizing the capacity, bandwidth, and power for the memory subsystem.

While the memory channel is capable of operating at other frequencies, any frequency that is lower then the maximum design point of the memory controller will result in lower bandwidth, higher latency and therefore lower performance.

In a general computer system, there may be a number of design tradeoffs that will result in a lower operating frequency in the memory subsystem.

These design tradeoffs include, but are not limited to, electrical loading due to memory capacity on the memory channels, power reduction in the memory devices that may result in operating the memory devices at a operating frequency lower then the maximum design point, and cost tradeoff's that result in a lower frequency at the memory device interface.

Thus, when the temperature within a memory device and / or the memory hub device rises past a predetermined temperature limit, the memory hub device may reduce the memory access rate to the memory device or all memory devices to reduce the power being used by the memory devices.

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