Cap removal for gate electrode structures with reduced complexity

Abstract

The present disclosure relates to manufacturing techniques and respective semiconductor devices in which the capping material of gate electrode structures may be removed together with portions of the capping material of resistors on the basis of a highly controllable directional etch process, wherein raised drain and source regions may be protected on the basis of a fill material.

Description

BACKGROUND1. Field of the Disclosure[0001]Generally, the present disclosure relates to semiconductor devices and respective manufacturing techniques in which transistor elements may be formed on the basis of a complex transistor architecture including raised drain and source regions in combination with gate electrode structures that need to be exposed in a moderately late manufacturing stage.2. Description of the Related Art[0002]Significant progress has been made in the field of semiconductor devices, such as integrated circuits, by continuously reducing the dimensions of the individual components, such as circuit elements in the form of transistor elements, capacitors, resistors and the like. For example, in currently available highly sophisticated integrated circuits, several hundred millions or more circuit elements, mainly transistor elements, may be formed on a single semiconductor chip, thereby offering the potential of integrating more and more functions into a single semico...

AI Technical Summary

Benefits of technology

The present disclosure describes a process for removing a capping material from gate electrode structures before incorporating a highly conductive metal semiconductor compound. The process is made more efficient by embedding the semiconductor device in an appropriate fill material, reducing material loss and the risk of generating critical device areas. The use of a plasma-assisted anisotropic etch process instead of a wet chemical etch chemistry reduces process complexity and failures. The previously provided fill material can also be used as an implantation mask for introducing additional implant species, providing additional degrees of freedom for adjusting overall transistor characteristics. The reduced height of the spacer elements after the capping material removal increases the process window and reduces material loss. The plasma-assisted process also reduces the risk of forming metal semiconductor compound bridges and reduces the number of process steps, achieving reduced manufacturing costs. The improved surface topography after the removal of the capping material allows for more efficient design rules and contact element formation in critical areas.

Problems solved by technology

For example, additional doping, counter-doping and the like may be applied in a spatially localized manner for basic semiconductor material, wherein any such “fine tuning” of various types of transistor elements would not be possible or would require significant efforts during previous manufacturing stages.

Images