Plasma thermal shield for heat dissipation in plasma chamber

Abstract

Methods of and apparatuses for dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a plasma thermal shield for a plasma processing chamber includes an annular ring body having an inner opening. A plasma-facing surface of the annular ring body has a general topography. A bottom surface of the annular ring body reciprocates the general topography with recessed regions disposed therein, providing one or more protruding regions at the bottom surface of the annular ring body.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS[0001]This application is a continuation of U.S. patent application Ser. No. 14 / 109,820, filed on Dec. 17, 2013, the entire contents of which are hereby incorporated by reference herein.BACKGROUND[0002]1) Field[0003]Embodiments of the present invention pertain to the field of semiconductor processing and, in particular, to methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits thereon.[0004]2) Description of Related Art[0005]In semiconductor wafer processing, integrated circuits are formed on a wafer (also referred to as a substrate) composed of silicon or other semiconductor material. In general, layers of various materials which are either semiconducting, conducting or insulating are utilized to form the integrated circuits. These materials are doped, deposited and etched using various well-known processes to form integrated circuits. Each wafer is processed to form a large number of individual regions co...

AI Technical Summary

Benefits of technology

The patent describes a method for cutting semiconductor wafers that contain many integrated circuits. The method involves putting the substrate, which has a patterned mask on top of it, in a plasma etch chamber with a shield to protect it from the plasma etching. The shield absorbs heat and helps to keep the substrate cool. The plasma etching then separates the integrated circuits by cutting through the streets of the substrate. This process helps to protect the substrate carrier which holds the substrate, and results in better quality wafers.

Problems solved by technology

One problem with either scribing or sawing is that chips and gouges can form along the severed edges of the dies.

In addition, cracks can form and propagate from the edges of the dies into the substrate and render the integrated circuit inoperative.

Chipping and cracking are particularly a problem with scribing because only one side of a square or rectangular die can be scribed in the direction of the crystalline structure.

Consequently, cleaving of the other side of the die results in a jagged separation line.

As a result of the spacing requirements, not as many dies can be formed on a standard sized wafer and wafer real estate that could otherwise be used for circuitry is wasted.

Furthermore, after cutting, each die requires substantial cleaning to remove particles and other contaminants that result from the sawing process.

Plasma dicing has also been used, but may have limitations as well.

For example, one limitation hampering implementation of plasma dicing may be cost.

A standard lithography operation for patterning resist may render implementation cost prohibitive.

Another limitation possibly hampering implementation of plasma dicing is that plasma processing of commonly encountered metals (e.g., copper) in dicing along streets can create production issues or throughput limits.

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