Interconnect Structures Incorporating Air-Gap Spacers

Abstract

A dual damascene article of manufacture comprises a trench containing a conductive metal column where the trench and the conductive metal column extend down into and are contiguous with a via. The trench and the conductive metal column and the via have a common axis. These articles comprise interconnect structures incorporating air-gap spacers containing metal / insulator structures for Very Large Scale Integrated (VLSI) and Ultra Large Scale Integrated (ULSI) devices and packaging. The trench in this regard comprises a sidewall air-gap immediately adjacent the side walls of the trench and the conductive metal column, the sidewall air-gap extending down to the via to a depth below a line fixed by the bottom of the trench, and continues downward in the via for a distance of from about 1 Angstrom below the line to the full depth of the via. In another aspect, the article of manufacture comprises a capped dual damascene structure.

Description

FIELD OF THE INVENTION[0001]The field of the invention comprises semiconductor device manufacturing and more specifically to methods of forming air-gap containing metal / insulator interconnect structures for Very Large Scale Integrated (VLSI) and Ultra Large Scale Integrated (ULSI) devices and packaging.BACKGROUND OF THE INVENTION[0002]Device interconnections in Very Large Scale Integrated (VLSI) or Ultra-Large Scale Integrated (ULSI) semiconductor chips typically have multilevel structures containing patterns of metal wiring layers encapsulated in an insulator. Wiring structures within a given level of wiring are separated by an intra level dielectric, while the individual wiring levels are separated from each other by layers of an inter level dielectric conductive vias are formed in the inter level dielectric to provide inter level contacts between the wiring traces.[0003]Because of their effects on signal propagation delays, the materials and layout of these interconnect structure...

AI Technical Summary

Benefits of technology

[0024]For damaged ILD widths of approximately >30 nm, for which the likelihood of subsequent cap deposition filling the air-gap created after the selective etch is high, we propose a second embodiment of the present invention. The relevant air-width could range from about 30 nm and larger. However, the exact limits depend on the cap deposition method and would be obvious to those skilled in the art. In the second embodiment, the cap layer is deposited following CMP. Perforations are made in the cap layer either by using an optical mask or by using a random self-assembled scheme as outlined by Colburn et al., U.S. Pat. No. 6,911,400. The size of the perforations are such they are big enough for the extraction of the damaged ILD and small enough such that pinch off occurs during cap or next level ILD deposition. The range of the cap perforations can range from, but not limited to, about 10 nm to about 80 nm. The extraction of the damaged ILD is done subsequent to this perforation step. This is followed by the deposition of a second cap layer during which the small perforations facilitates a quick pinch off hence preventing deposition of the cap material inside the air-gaps.

Problems solved by technology

Because of their effects on signal propagation delays, the materials and layout of these interconnect structures can substantially impact chip speed, and thus chip performance.

This is generally very difficult to achieve.

This is an undesirable structure since it could lead to high field concentrations around the curved parts and poor breakdown behavior of the interconnect, a significant drawback.

This makes their scheme very expensive and limits the performance due to their inability to extend the air-gap below the trench to obtained increased performance.

Finally, in their scheme, they use plasma based methods to remove the dielectric spacer to form the air-gap and they do this with the metal interconnect already present in the structure which could lead to a degradation of the conductive properties of the interconnect.

The other drawbacks mentioned above for U.S. Pat. No. 6,228,763 still remain, the chief of which is that this is based on a single damascene integration scheme which is prohibitively expensive, limited in performance, and not extendible readily to any interconnect scheme in the industry which uses Cu based metallurgy.

This is very difficult to achieve, especially as the structure gets closer to the tens of nanometer dimensions because this calls for a lithography process where the pitch remains the same but the openings are enlarged by twice the spacer width which makes the lithography process difficult to employ.

In addition, due to the lack of a gap below the trench and adjacent to the vias, their performance gain is limited.

Finally, since their invention calls for an extra lithography step, in addition to extra wet / SC CO2 etches to remove the damaged dielectric, it is very expensive to practice.

In addition structures with air-gaps may not be as uniformly planar as structures built with intrinsically more rigid solid dielectrics.

This can be a problem if locally depressed areas are formed by bridge layer sag over unsupported air-gaps, since metal filling these depressed areas will remain in the structure after chemical-mechanical polishing (CMP) and be a source of shorts and / or extra capacitance.

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