Method and apparatus for reducing flicker noise in a semiconductor device

Abstract

Some embodiments discussed relate to an integrated circuit and methods for making it, comprises a semiconductor substrate and a plurality of fins disposed on the semiconductor substrate and a gate insulator disposed on the plurality of fins and a gate stack disposed on the gate insulator and the plurality of fins are implanted by a dopant.

Description

RELATED APPLICATIONS[0001]This patent application claims the benefit of priority, under 35 U.S.C. Section 119(e), to U.S. Provisional Patent Application No. 60 / 813,630, filed on Aug. 30, 2006, which is incorporated herein by reference.TECHNICAL FIELD[0002]Embodiments described herein relate generally to semiconductor devices and more particularly, to field-effect transistors (FETs) and methods of fabricating the same.BACKGROUND[0003]Flicker noise is a dominant noise source in metal oxide semiconductor field-effect transistor (MOSFET) devices at low frequencies. In battery-driven circuits where signal-to-noise ratio cannot be improved at the cost of power consumption, a reduction of flicker noise is desired.BRIEF DESCRIPTION OF THE DRAWINGS[0004]FIG. 1A-1E illustrate a sequence of cross-sectional drawings of a partially completed semiconductor wafer showing some embodiments of a method of fabrication of a semiconductor device having a dopant implanted into silicon fins.[0005]FIG. 2 i...

AI Technical Summary

Problems solved by technology

Another effect that influences flicker noise is surface roughness.

The lower binding energy of H2 compared to fluorine leads to stronger increase of flicker noise under hot carrier stress.

Low-quality native oxide grows relatively quick and is a problem in achieving very thin high-quality gate oxides.

Smaller thicknesses could lead to higher gate leakage currents and larger thicknesses could require gate voltages above 5 V. Neither of these scenarios are desirable and hence not used in battery-driven systems.

Flicker noise is a design constraint that limits complimentary metal oxide semiconductor (CMOS) RF and analog circuit performance with respect to signal-to-noise ratio in low-noise amplifiers (LNA), noise contribution of direct down conversion mixers and phase noise of voltage-controlled oscillators (VCO).

In some embodiments, metal gates provide low diffusivity towards dopants such as fluorine and consequently implantation of fluorine into gate insulators is prohibited using conventional methods.

Implantation of fluorine in the drain and source regions with a high dose after gate insulator growth and prior to the source / drain anneal step has the disadvantage of increasing junction capacitance (in bulk CMOS) and increasing dramatically junction leakage current.

Furthermore, embodiments of the disclosed method prevent high junction leakage that increases standby power consumption which is an important drawback for battery-driven systems.

Due to this boron diffusion an unwanted reduction of threshold voltage occurs.

Such an approach is inefficient because fluorine gets incorporated at the silicon oxide interface (“fluorine pile-up” in secondary-ion mass spectrometry (SIMS) profiling) of two interfaces exist above and below the buried oxide.

Furthermore, plasma fluoridation is difficult to apply to finFETs and Multi-gate FETs due to the vertical structure of the fins.

Use of nitrided silicon oxide can lead to higher flicker noise compared to pure silicon oxide depending on the nitridation process.

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