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Memory system and method for controlling the same, and method for maintaining data coherency

a memory system and memory technology, applied in the field of memory system and a control method of the memory system, can solve the problems of increasing the latency of the device and the memory system, providing slower access performance, and reducing the utilization rate of the bus, so as to improve the efficiency of memory access

Inactive Publication Date: 2007-08-09
IBM CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

[0007] An object of the present invention is to improve the efficiency...

Problems solved by technology

While such memories (system memories) configured as DRAMs have a large storage capacity, they provide slower access performance.
This means that additional operational delay due to a snoop hit on the write access decreases the bus utilization rate and increases the...

Method used

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  • Memory system and method for controlling the same, and method for maintaining data coherency
  • Memory system and method for controlling the same, and method for maintaining data coherency
  • Memory system and method for controlling the same, and method for maintaining data coherency

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Embodiment Construction

[0016] The present invention will be described with reference to the accompanying drawings. FIG. 2 is a diagram for illustrating an overview of a method (operation) of the present invention. In FIG. 2, a CPU bus 10 and a system bus 12 is interconnected through a bus bridge 13. Coupled onto the CPU bus 10 are CPU #0 (13) and CPU #2 (14). Each of the two CPUs has a cache. Coupled onto the system bus 12 are a device #2 (15), a memory controller (16) and a memory (17). The memory (17) is a system memory such as a DRAM. The memory controller (16) has a buffer 20 for temporarily storing data. While the configuration in FIG. 2 includes the two buses, the CPU bus 10 and system bus 12, a configuration in which devices are coupled onto one system bus may be used. Furthermore, any number of devices may be connected to a bus, provided that at least two master devices that can occupy the bus are connected to the bus.

[0017] In a snooping algorithm, CPU #0 (13) having a cache monitors (snoops 19)...

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Abstract

A memory system including a bus 10, 11, a memory 17, a memory controller 16, a first device 13 having a cache, and a second device 15, all connected to the bus, wherein the memory controller includes a buffer 20 for temporarily storing cache data and write data that the second device writes in the memory. The buffer of the memory controller temporarily stores cached data and the write data to be written on write access to the memory by the second device, which enables maintenance of data coherency while avoiding a write access retry by the second device.

Description

FIELD OF THE INVENTION [0001] The present invention generally relates to a memory system and a method for controlling the memory system and, in particular, to a method for improving the efficiency of write access to a memory through a bus while maintaining data coherency. BACKGROUND OF THE INVENTION [0002] In personal computers systems (PCs), a CPU and a memory (such as a DRAM) are interconnected through a bus. Each device acts as a master device (bus master) to access the memory in which data is stored. While such memories (system memories) configured as DRAMs have a large storage capacity, they provide slower access performance. In order to achieve faster access to frequently used data, a CPU uses a cache memory (hereinafter “cache”) implemented by a memory such as an SRAM. Although a cache has a smaller storage capacity than a DRAM system memory, it can provided faster access then DRAM system memory. [0003] In a system having a cache, coherency between the cache and the main memo...

Claims

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Application Information

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IPC IPC(8): G06F12/00
CPCG06F12/0835
Inventor HARADA, NOBUYUKI
Owner IBM CORP
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