Superhard cutters and associated methods

Abstract

A cutting device comprises a base having a working side that is oriented to face a workpiece from which material is to be removed. A plurality of individual cutting elements are arranged on the working side of the base, with each cutting element having a peak that comprises at least one cutting edge that is formed from a polycrystalline superhard material. The peaks of the cutting elements are aligned in a common plane.

Description

PRIORITY DATA [0001] This application claims priority to copending U.S. Provisional Patent Application No. 60 / 681,798, filed May 16, 2005, which is hereby incorporated herein by reference in its entirety.FIELD OF THE INVENTION [0002] The present invention relates generally to cutting devices used to plane workpieces formed of various materials. Accordingly, the present invention involves the fields of chemistry, physics, and materials science. BACKGROUND OF THE INVENTION [0003] It is estimated that the semiconductor industry currently spends more than one billion U.S. Dollars each year manufacturing silicon wafers that exhibit very flat and smooth surfaces. Typically, chemical mechanical polishing (“CMP”) is used in the manufacturing process of semiconductor devices to obtain smooth and even surfaced wafers. In a conventional process, a wafer to be polished is generally held by a carrier positioned on a polishing pad attached above a rotating platen. As slurry is applied to the pad ...

AI Technical Summary

Benefits of technology

[0011] In accordance with another aspect of the invention, a product is provided that can be formed by the process comprising: engaging a surface of a workpiece with a plurality of individual cutting elements of a cutting device, the individual cutting elements being integrally formed from a working side of an integral piece of a polycrystalline superhard material and each cutting element having a peak that is aligned in a common plane; and moving the workpiece and the cutting device relative to one another to thereby remove material from the workpiece with the cutting elements.

Problems solved by technology

While this well-known process has been used successfully for many years, it suffers from a number of problems.

For example, this conventional process is relatively expensive and is not always effective, as the silicon wafers may not be uniform in thickness, nor may they be sufficiently smooth, after completion of the process.

In addition to becoming overly “wavy” when etched by a solvent, the surface of the silicon wafers may become chipped by individual abrasive grits used in the process.

Moreover, if the removal rate is to be accelerated to achieve a higher productivity, the grit size used on the polishing pad must be increased, resulting in a corresponding increase in the risk of scratching or gouging expensive wafers.

Furthermore, because surface chipping can be discontinuous, the process throughput can be very low.

Consequently, the wafer surface preparation of current state-of-the-art processes is generally expensive and slow.

While diamond grid pad conditioners have been effectively used in dressing CMP pads for polishing previous designs of integrated circuitry, they have not been found suitable for making cutting-edge devices with nodes smaller than 65 nm.

This is because, with the decreasing size of the copper wires, non-uniform thickness due to rough- or over-polishing will change the electrical conductivity dramatically.

However, the more delicate the polishing process becomes, the higher the risk of scratching the surface of the wafer becomes.

Otherwise, the protrusion of a few “killer asperities” can ruin the polished wafer.

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