TFT array substrate and fabrication method thereof
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[0064] Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings.
[0065]FIG. 4 is a plan view of a TFT array substrate according to the present invention, and FIG. 5 is a sectional view taken along line II-II′ of FIG. 4.
[0066] Referring to FIGS. 4 and 5, the TFT array substrate includes a gate insulating layer 112 on a lower substrate 101, a TFT 130 formed at each crossing portion, a pixel electrode 122 formed in a pixel region 105 defined by the crossing gate and data lines, and a channel passivation layer 120 for protecting the TFT 130.
[0067] Also, the TFT array substrate further includes a storage capacitor 140 formed by an overlapping portion of the gate line 102 and the pixel electrode 122, a gate pad 150 connected to the gate line 102, and a data pad 160 connected to the data line 104 by a jumping structure. The gate line 102 that supplies a gate signal and the data line 104 that...
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