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Silicon chip carrier with conductive through-vias and method for fabricating same

a silicon chip and through-via technology, applied in semiconductor devices, semiconductor/solid-state device details, electrical apparatuses, etc., can solve problems such as inability to control dimensional tolerances, material limitations, and inability to manufacture, and achieve the effects of reducing the number of through-vias

Inactive Publication Date: 2006-02-09
GLOBALFOUNDRIES INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Problems have arisen in carriers of the prior art due to limitations in materials, deposition methods, control of dimensional tolerances, and mechanical stresses encountered during processing of the materials.
As SOC integration density demands increase and speed continues to increase, power densities become untenable.
Current packaging technologies are limited in interconnect density, I / O density, interconnect bandwidth, and chip-to-chip spacing required to reach the ultrahigh performance levels needed, including greater than 10 GHz chip-to-chip communications with full memory bandwidth for >1000 I / Os per chip-to-chip edge interconnection.
It is not possible for current off-chip devices to respond at the on-chip frequencies needed, due to excessive distances from the chip, high parasitic impedance, and slow characteristics of the devices themselves.
Filling high aspect ratio vias, with a height in the range of a single μm to several hundred μms with diameters of several 10's to ˜100 μm, to provide packages with through-vias, is challenging.
However, the hydrodynamics, the ionic concentrations, and the diffusivities limit the filling of deep blind holes.
(ECTC 2002) did extensive plating optimization and were still not able to eliminate voids in vias of only 70 μm deep.
Methods for filling large blind holes which are to be opened later break down or become impractical at such dimensions.
The Black method provides adequate fill of the through-vias (for some of the listed materials); however, given the materials used, the resulting structure will experience the mechanical failures described below with reference to Table 1.
Gaul utilizes materials that are more closely thermally matched, namely W and poly-Si, but would not have practical deposition methods for multi-10's of pin and would have vastly differing values for modulus.
It is also to be noted that incorporation of embedded components into present carriers is difficult due to processing limitations, such as high temperature sintering conditions for ceramic carriers, as well as limitations with embedded component material systems.
At the above-stated diameters, most metals which are commonly used for integrated circuit interconnect vias generate unacceptable stress levels on the carrier layer material (e.g., Si or glass) due to thermal expansion mismatch.
In addition, the metal structures exhibit top surface extrusions, ruptures, or expansions during and after typical thermal cycling.
For carrier substrates and integrated devices that are comprised of brittle materials, such as semiconductors, glass, or ceramics, the risk of mechanical failure by brittle fracture is significant given the thermal expansion mismatches and the fragility of the carrier materials.
In addition to brittle fracture, interfacial delamination is likely when employing standard materials and combinations of materials at the stated dimensions.
However, the modulus of W is so high (>400 GPa) compared to that of silicon (˜170 GPa) that brittle fracture of the Si and / or delamination of via sidewalls are likely, given the finite but small thermal expansion mismatch.
Like W, the typical processes used to grow or deposit poly-Si are only practical for thicknesses up to ˜1 or several single μm, and often are limited to deposition temperatures above the maximum temperatures that can be tolerated by integrated circuit components or wiring on the substrate above (if these are to be fabricated prior to filling the through-vias).
Three potential problems associated with large CTE mismatches between vias and the Si substrate include delamination at the via sidewalls (resulting in so-called “rattling vias” that exhibit compromised conductivity and mechanical stability), cracking of the Si substrate between vias, and piston-like ruptures of any overlying or underlying structures or thin films in contact with the top and bottom surfaces of the vias.

Method used

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  • Silicon chip carrier with conductive through-vias and method for fabricating same
  • Silicon chip carrier with conductive through-vias and method for fabricating same
  • Silicon chip carrier with conductive through-vias and method for fabricating same

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second embodiment

[0048]FIG. 5 is a flow chart of a representative process flow for fabricating a carrier with through-vias, as shown in FIG. 2B, in accordance with the present invention. At step 500, blind vias are etched into the substrate, as above, to a depth which is slightly greater than the desired depth of the through-vias in the finished product. At step 502, the sidewalls of the blind vias are insulated (as above), preferably by oxidizing silicon to form a thin layer of SiO2 or PECVD oxide or nitride or both. An annular fill is conducted at step 504 to provide metal (e.g., PVD TaN / Ta / Cu plus plated Cu to thickness ˜ 1 / 10 to ·⅕ of the via diameter) along the exposed insulated surfaces of the blind via. The top of the via is then capped with metal by either an overfilling, burnishing, or similar technique. The void in the center of the via will contain the ambient of the capping process, typically N2 or a vacuum. Overfilling is achieved by a PVD, CVD, evaporation, or sputtering process for me...

third embodiment

[0051]FIG. 7 is a flow chart of a representative process flow for fabricating a carrier with through-vias, as shown in FIG. 2C, in accordance with the present invention. At step 700, blind vias are etched into the substrate to a depth which is the desired depth of the through-vias in the finished product. The vias are etched in a pattern whereby each is an annular via of thickness ˜ 1 / 10 to ˜⅕ of the via diameter etched about a post of substrate material which will remain as the core of the via. At step 702, the sidewalls of the blind vias are insulated, preferably by oxidizing silicon to form a thin layer of SiO2 (see above) on both the outer sidewalls and the post sidewalls. The annular vias are then overfilled with the desired conductive material at step 704. Thereafter, the top of the structure is planarized at step 708 to remove excess metal at the top surface and to expose the substrate between the annular metal rings of the vias. IC circuits or components may be fabricated on...

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Abstract

A carrier structure and method for fabricating a carrier structure with through-vias each having a conductive structure with an effective coefficient of thermal expansion which is less than or closely matched to that of the substrate, and having an effective elastic modulus value which is less than or closely matches that of the substrate. The conductive structure may include concentric via fill areas having differing materials disposed concentrically therein, a core of the substrate material surrounded by an annular ring of conductive material, a core of CTE-matched non-conductive material surrounded by an annular ring of conductive material, a conductive via having an inner void with low CTE, or a full fill of a conductive composite material such as a metal-ceramic paste which has been sintered or fused.

Description

FIELD OF THE INVENTION [0001] The invention relates generally to a carrier for mounting and packaging multiple integrated circuit chips; and, more particularly, to a self-supporting semiconductor or insulator carrier substrate with conductive through-vias. BACKGROUND OF THE INVENTION [0002] A carrier for integrated circuit devices is typically fabricated of semiconductor, glass, or glass-ceramic material as a freestanding substrate, chip or wafer having conductive through-vias. The through-vias are exposed on the top and underside of the carrier and are insulated from each other. Multiple levels of carrier material with metallic or semi-metallic vias are often required to obtain the necessary conductive paths between chips and other devices mounted with respect to the carrier. The carrier having through-vias provides chip input / output terminals (I / O), with the chips typically mounted in the “flip chip” manner, and other device I / O through the carrier from the surface at which the ch...

Claims

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Application Information

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Patent Type & Authority Applications(United States)
IPC IPC(8): H01L23/48H01L21/48H01L21/768H01L23/498
CPCH01L21/486H01L21/76898H01L2924/10253H01L23/49827H01L23/49883H01L2224/16H01L2924/01004H01L2924/01078H01L2924/01079H01L2924/09701H01L2924/15311H01L2924/3011H01L2924/3025H01L2924/01019H01L2924/01322H01L2924/00
Inventor EDELSTEIN, DANIEL CHARLESANDRY, PAUL STEPHENBUCHWALTER, LEENA PAIVIKKICASEY, JON ALFREDGOMA, SHERIF A.HORTON, RAYMOND R.HOUGHAM, GARETH GEOFFREYLANE, MICHAEL WAYNELIU, XIAO HUPATEL, CHIRAG SURYAKANTSPROGIS, EDMUND JURISSTEEN, MICHELLE LEIGHSUNDLOF, BRIAN RICHARDTSANG, CORNELIA K.WALKER, GEORGE FREDERICKCHENG, YU-TINGOCHELTREE, KENNETH BLAIRMONTOYE, ROBERT K.
Owner GLOBALFOUNDRIES INC
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