Random access memory

Abstract

A process for enhancing refresh in Dynamic Random Access Memories wherein n-type impurities are implanted into the capacitor buried contact after formation of the access transistor components. The process comprises forming a gate insulating layer on a substrate and a transistor gate electrode on the gate insulating layer. First and second transistor source / drain regions are formed on the substrate adjacent to opposite sides of the gate electrodes. N-type impurities, preferably phosphorous atoms, are then implanted into the first source / drain region which will serve as the capacitor buried contact.

Description

FIELD OF THE INVENTION [0001] The invention relates generally to the formation of integrated circuit devices and more particularly to a process for enhancing refresh in Dynamic Random Access Memory devices (DRAMs). BACKGROUND OF THE INVENTION [0002] Generally, integrated circuits are mass produced by forming many identical circuit patterns on a single silicon wafer, which is thereafter cut into many identical dies or “chips.” Integrated circuits, also commonly referred to as semiconductor devices, are made of various materials that may be electrically conductive, electrically nonconductive (insulators) or electrically semiconductive. Silicon, in single crystal or polycrystalline form, is the most commonly used semiconductor material. Both forms of silicon can be made electrically conductive by adding impurities. The introduction of impurities into silicon is commonly referred to as doping. Silicon is typically doped with boron or phosphorus. Boron atoms have one less valence electro...

AI Technical Summary

Benefits of technology

[0011] One object of the invention is to enhance refresh in dynamic access memory devices.

[0012] Another object is to alleviate refresh degradation associated with the miniaturization of memory cell components and decreased operating voltages.

[0013] Another object is to lessen the adverse effect that contact misalignment and junction leakage may have on refresh.

[0017] The process of the invention, implanting impurities into the capacitor buried contact after formation of the source / drain regions, thus enhances refresh of the memory cell by, it is believed, eliminating one or more defects in the cell.

Problems solved by technology

If the cell is not refreshed before losing a threshold level of charge, then the cell will fail, i.e., lose the bit of information stored therein.

And, if a cell fails, then the chip itself is defective and cannot be used.

Further, increased packing densities and corresponding cell miniaturization increases refresh degradation due to trap assisted tunneling, micro zenering and other such refresh loss mechanisms.

Hence, proper alignment of the contacts formed in these corridors becomes more difficult.

Although this process substantially reduces the risk of contact misalignment and, incidentally, may lessen refresh degradation associated therewith, it does not address refresh problems associated with lower operating voltages or junction leakage.

As with the Dennison patent, Hsu does not address the problems of refresh degradation in general, and specifically with regard to refresh degradation associated with junction leakage, lower device operating voltages, and misalignment of the contact between the polysilicon capacitor bottom electrode and the transistor source / drain.

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