Semiconductor device with elevated source/drain structure and its manufacture method

Abstract

A gate electrode is formed over a partial surface area of a semiconductor substrate, with a gate insulating film being interposed therebetween. A first semiconductor film is formed over the semiconductor substrate on both sides of the gate electrode, the first semiconductor film being spaced apart from the gate electrode. An impurity diffusion region is formed in each of the first semiconductor films. An extension region is formed in the surface layer of the semiconductor substrate on both sides of the gate electrode. The extension region is doped with impurities of the same conductivity type as the impurity diffusion region and being connected to a corresponding one of the impurity diffusion regions. Sidewall spacers are formed on the sidewalls of the gate electrode, the sidewall spacers extending beyond edges of the first semiconductor films on the gate electrode side and covering partial surfaces of the first semiconductor films.

Description

CROSS REFERENCE TO RELATED APPLICATION [0001] This application is based on and claims priority of Japanese Patent Application No. 2002-251268 filed on Aug. 29, 2002, the entire contents of which are incorporated herein by reference. BACKGROUND OF THE INVENTION [0002] A) Field of the Invention [0003] The present invention relates to a semiconductor device and its manufacture method, and more particularly to a MOS semiconductor device having an elevated source / drain structure and its manufacture method. [0004] B) Description of the Related Art [0005] High speed operation and high integration of semiconductor devices require a shortened gate length and a reduced parasitic capacitance. In order to suppress the short channel effects, it is necessary to shallow source and drain regions. In order to suppress an increase in a sheet resistance to be caused by shallow source and drain regions, techniques of forming a refractory metal silicide layer on the source and drain regions are adopted....

AI Technical Summary

Benefits of technology

The present invention provides a semiconductor device with an elevated source / drain structure that can mitigate the short channel effects. The method includes steps of forming a gate insulating film and a gate electrode on a semiconductor substrate, growing semiconductor films on the substrate, and then implanting impurities to form the source and drain regions. The method also includes steps of forming side wall spacers on the gate electrode, and using the side wall spacers as a mask to prevent lateral diffusion of impurities. The elevated source / drain structure formed through selective epitaxial growth can also help to prevent aggregation of metal silicide. The technical effects of the invention include improved performance and reliability of semiconductor devices.

Problems solved by technology

If the refractory metal silicide layer is formed on the shallow source and drain regions, junction leak current increases.

Since the growth temperature cannot be made high, the growth speed of the semiconductor film is slow.

This method is not suitable for mass production.

If the heat treatment temperature is set to 600° C. or lower, the sufficient effects of removing the native oxide film cannot be expected.

The sufficient short channel suppression effects cannot therefore be expected.

Further, since the heat treatment for diffusing impurities in the extension regions is preformed after the titanium silicide layer is formed, aggregation of titanium silicide is likely to occur.

A low resistance of the gate electrode cannot therefore be expected.

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