Adhesion between dielectric materials

Abstract

The present invention discloses a method including: determining whether a surface of a dielectric layer is reactive; activating the surface if the surface is not reactive; performing a cycle on the surface, the cycle including: reacting the surface with a metal; and activating the metal. The present invention also discloses a structure including: a substrate; a first interlayer dielectric located over the substrate; a first adhesion promoter layer located over the first interlayer dielectric; an etch stop layer located over the first adhesion promoter layer; a second adhesion promoter layer located over the etch stop layer; and a second interlayer dielectric located over the second adhesion promoter layer.

Description

[0001] 1. Field of the Invention[0002] The present invention relates to the field of semiconductor integrated circuit (IC) manufacturing, and, more specifically, to a method of improving adhesion at an interface between dielectric materials, as well as, a structure including an adhesion promoter layer at the interface between dielectric materials.[0003] 2. Discussion of Related Art[0004] Gordon Moore first suggested in 1965 that the pace of technology innovation would double the number of transistors per unit area on a chip every 18 months. Over the ensuing decades, the semiconductor industry has adhered closely to Moore's Law in improving device density.[0005] Maintaining such an aggressive schedule for each device generation has required continual enhancements at the corresponding technology node. Additive processes using ion implantation, annealing, oxidation, and deposition had to be enhanced to deliver the requisite doping profiles and film stacks. Subtractive processes using p...

AI Technical Summary

Benefits of technology

"The present invention relates to a method and structure for improving adhesion at the interface between dielectric materials in semiconductor manufacturing. The method involves activating the surface of a dielectric material and reacting it with a metal to form a very thin layer of an adhesion promoter. This adhesion promoter layer can improve the yield and reliability of the chip by minimizing variations in topography across the chip. The method can be carried out using various techniques such as chemical vapor deposition or atomic layer deposition. The structure includes a very thin adhesion promoter layer, such as metal oxide, at the interface between an interlayer dielectric and an etch stop layer or hard mask. The invention can help to improve adhesion and performance of the chip by addressing the challenge of achieving proper adhesion at the interface between dielectric materials."

Problems solved by technology

The scaling down of transistors and wiring to comply with Moore's Law may degrade the performance and reliability of the chip if it is not accomplished properly.

For example, the switching speed of the transistors may be adversely impacted if the resistance-capacitance (RC) product delay in the wiring is too large.

However, adhesion at an interface between two dielectric materials may be inadequate, resulting in poor yield at assembly and packaging from cracking and delamination.

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