A MOS FET tube and its manufacturing method

Abstract

This invention discloses one MOS field effect tube and its process method, which has side wall bottom concaved toward inside. The field effect tube method comprises the following steps: a, injecting well ions for annealing to sacrifice oxidation layer peeling off; b, growing or depositing one layer of thick oxidation layer; c, processing total etching in middle area oxidation; d, growing grating oxidation; e, depositing multiple transistor grating; f, processing light etch on thick oxidation area; g, regular steps after etching.

Description

technical field [0001] The invention relates to a semiconductor manufacturing process, in particular to a MOS field effect transistor and a manufacturing method thereof. Background technique [0002] A cross-sectional structure diagram of an existing MOS field effect transistor is shown in FIG. 1 . In MOS field effect transistors, there will be parasitic capacitance between the gate-drain / source. As shown in FIG. 2, the parasitic capacitance includes gate to drain overlap capacitance (hereinafter referred to as C ovl ) and gate todrain fringing capacitance (hereinafter referred to as C fringing ). In the conventional semiconductor manufacturing process flow of the prior art, the sidewall of the gate is generally vertical and flat, and the parasitic capacitance of the MOS field effect transistor with the existing structure is usually relatively large. Parasitic capacitance usually affects the speed performance of digital circuits. The larger the capacitance, the worse th...

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Problems solved by technology

[0003] The parasitic capacitance between the gate drain / source of the MOS field effect transistor manufactured by the method of manufacturing MOS field effect transistor in the prior art is relatively large, which will affect the speed performance of the digital circuit

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