Manufacturing process of self-aligned silicide barrier layer

Abstract

This invention discloses one process method for automatic self-calibrating silicon block layer, which comprises the following steps: firstly growing first layer of silica dioxide by use of CVD method; then using HDP method to grow second layer of silica dioxide on the first layer of silica dioxide layer. The invention can solve the stuff ability problem between calibration block layer and multiple transistor lines to overcome the whole phenomenon to lower leakage current.

Description

technical field [0001] The invention relates to a manufacturing process method of a semiconductor integrated circuit, in particular to a manufacturing process method of a self-aligned silicide barrier layer. Background technique [0002] With the development of integrated circuits, the polysilicon line width and the spacing between line widths are becoming narrower and narrower, which has more and more implications for the filling ability of salicide blocks between polysilicon lines. Come higher demands. When the filling capacity is insufficient, a situation as shown in FIG. 1 arises, and voids are generated between polysilicon lines due to insufficient filling capacity. [0003] At the same time, due to the consideration of the filling ability, it is required that the grown salicide barrier layer should be as thin as possible, but this will inevitably cause pinholes, which will affect the device. As shown in FIG. 2, the pinhole phenomenon due to the formation of the thin ...

AI Technical Summary

Problems solved by technology

[0004] The technical problem to be solved by the present invention is to provide a method for manufacturing a self-aligned silicide barrier layer, which can solve the problem of the filling capacity of the self-aligned silicide barrier layer between polysilicon lines, and effectively overcome the pinhole phenomenon. Reduce leakage current

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