Semiconductor memory

Abstract

A first amplifier amplifies voltage of a first local bit line connected to static memory cells. Precharging circuits for precharging a first global bit line connected to an output of the first amplifier supply a precharging current through both ends of the first global bit line, respectively. Since the precharging current flows through the first global bit line in both directions, electromigration criteria can be made looser than in cases where the current flows in one direction. This makes it possible to avoid a defect which occurs due to electromigration of the first global bit line. Since the first global bit line can be reduced in wiring width, it is possible to minimize the layout area. As a result, the semiconductor memory can be reduced in chip size with a reduction in chip cost.

Description

technical field [0001] The present invention relates to semiconductor memories with static memory cells. In particular, the present invention relates to semiconductor memories having hierarchically structured bit lines. Background technique [0002] As transistor structures become finer and finer, the storage capacity of semiconductor memories is also increasing. At the same time, as the structure of transistors becomes finer, the operating frequency of logic LSIs such as microcomputers continues to increase. In order to increase the operating frequency, the access time of the semiconductor memory is required to be shorter. DRAMs and such semiconductor memories have a hierarchical structure of bit lines in view of reduced access times. In order to meet the need for further acceleration, it has recently been considered to employ hierarchy even in the wiring structure of bit lines in a semiconductor memory having static memory cells (hereinafter referred to as SRAM). [00...

AI Technical Summary

Problems solved by technology

Therefore, there is a problem that widening the wiring width of the global bit line may lead to an increase in chip size and chip cost

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