Crystal covered chip and crystal covered package substrate

Abstract

A crystal covered chip consists of several core powder sources and earthing weld pads, at least one signal weld pad ring, at least one power source weld pad ring and at least one earthing weld pad ring, all of which are configurated on the active surface of the crystal covered chip and the said weld pad rings are distributed in concentric ring like around the periphery of these earthing weld pads for core powder sources by using these core power sources / earthing weld pads as a centre. In addition, a crystal covered packaging substrate has several lug pads at the most top layer of wire layers, which has the positions corresponding to the positions of weld pads for the crystal covered chip seperately. A lug pad ring of nonsignal can be configurated at the periphery of lug pad ring and a pair of power source trace or earthing trace as the protective trace for signal trace can be configurated at both sides of a signal trace separately on an any wire layer in the crystal covered packaging substrate.

Description

technical field [0001] The present invention relates to a flip chip and a flip chip package substrate, and more particularly to a flip chip with a plurality of pad rings, and a flip chip corresponding to the above flip chip with a plurality of bumps. Flip Chip Package Substrate with Block Spacer Ring. Background technique [0002] Flip Chip bonding technology (Flip Chip, FC) is a common chip packaging technology used in chip scale packaging (Chip Scale Package, CSP), which mainly uses the arrangement of the area array (Area Array), the chip ( A plurality of die pads of die) are designed to be arranged on the active surface of the chip (active surface), that is, the side of the chip with active components (active device), and bumps (bumps) are respectively formed on each pad, and then Then, the bumps on the chip are connected to the corresponding contacts on the carrier, so that the chip is correspondingly bonded to the surface of the carrier in a flipping manner. [0003] ...

AI Technical Summary

Problems solved by technology

It should be noted that, since the known signal pads 114a, power pads 114b and ground pads 114c are irregularly distributed on the active surface 112 of the chip 110, when the original pads on the chip 110 (not (shown) When redistributed on the active surface 112 of the chip 110 through the redistribution layer (Re-Distribution Layer, RDL) (not shown), the original pads of the chip 110 will be relatively increased after being reconfigured by winding The line length of the bonding pad 114, thereby increasing the signal transmission path length, thereby reducing the electrical performance of the chip 110 (Electrical Performance)

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