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Semiconductor device with shallow-channel isolation structure and its preparing process

An isolation structure and semiconductor technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, electric solid-state devices, etc., can solve problems such as difficult to maintain P-FET characteristics and difficult to maintain device characteristics at the same time

Inactive Publication Date: 2004-09-29
SAMSUNG ELECTRONICS CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

As a result, it is difficult to maintain the characteristics of the P-FET
[0015] Therefore, if the sidewall oxide layer in each region is formed to have a uniform thickness, it is difficult to simultaneously maintain the excellent device characteristics of the N-FET in the element region and the P-FET in the core region and the peripheral region

Method used

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  • Semiconductor device with shallow-channel isolation structure and its preparing process
  • Semiconductor device with shallow-channel isolation structure and its preparing process
  • Semiconductor device with shallow-channel isolation structure and its preparing process

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0034] First, refer to Figure 3A , a masking pattern 22 is formed on the semiconductor substrate 20 to expose a region for device isolation. The semiconductor substrate 20 containing predetermined impurities is defined as an element region in which a memory device will be formed and a core region in which a P-FET will be formed, and a peripheral region. exist Figure 3A In , the element area A1 and the core and peripheral area A2 are shown. Masked pattern 22 may be formed of a material that has a very low etch selectivity relative to silicon and is resistant to oxidation. For example, masked pattern 22 may be a stack of silicon oxide and silicon nitride layers.

[0035] Then, using the masked pattern 22 as a mask, the semiconductor substrate 20 is dry etched to a predetermined depth. As a result, a first trench T1 and a second trench T2 are formed in the semiconductor substrate 20 . Here, the first and second trenches T1 and T2 are shallow trenches for forming shallow tr...

Embodiment 2

[0045] The second preferred embodiment of the present invention is the same as the first embodiment described above from the process of forming the trenches T1 and T2 to the process of forming the thermal oxide layer 24 . Therefore, only the processes after forming the thermal oxide layer 24 will be described.

[0046] First, refer to Figure 5A , and form a photoresist pattern 26 through a photolithography process to expose the element region A1. Thereafter, the thermal oxide layer 24 in the exposed element region A1 is etched by isotropic etching. At this time, the thermal oxide layer 24 is etched to leave a predetermined thickness in the second trench T2. The silicon semiconductor substrate 20 is hydrophobic and thus easily damaged by isotropic etching. Thus, a thermal oxide layer 24 remains to prevent such damage. Here, reference numeral 24a denotes a thermal oxide layer etched to a predetermined thickness.

[0047] Thereafter, if Figure 5B As shown, the photoresist...

Embodiment 3

[0051] Up to the process of forming trenches T1 and T2, the third preferred embodiment is the same as the first embodiment. Therefore, only the processes after forming the trenches T1 and T2 will be described.

[0052] refer to Figure 6A , the first sidewall oxide layer 40 is formed by thermally oxidizing the inner surfaces of the trenches T1 and T2. At this time, the first sidewall oxide layer 40 is formed with a thickness capable of preventing sustain current from being generated in the P-FET in the core region and the peripheral region A2. That is, the first sidewall oxide layer 40 should be formed with a thickness capable of preventing electrons trapped in the inner liner, which is formed by a subsequent process, from penetrating into the semiconductor substrate, for example, the thickness is 100-300 Å.

[0053] Then, if Figure 6BAs shown, a photoresist pattern 26 is formed by a known photolithography process to mask the core and peripheral area A2. Thereafter, the f...

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Abstract

A semiconductor device having a shallow trench isolation (STI) structure, which is capable of reducing leakage current in a P-FET and improving the device characteristics of a memory device, and a manufacturing method thereof, including a semiconductor substrate having a first area with a first trench formed therein and a second area with a second trench formed therein; a first sidewall oxide layer formed on the inner surface of the first trench; a second sidewall oxide layer, which is thinner than the first sidewall oxide layer, formed on the inner surface of the second trench; a liner formed on the surfaces of the first and second sidewall oxide layers; and a dielectric material that fills the first and second trenches.

Description

technical field [0001] The present invention relates to a semiconductor device with an isolation layer and a manufacturing method thereof, more particularly, to a semiconductor device with a shallow trench isolation structure and a manufacturing method thereof. Background technique [0002] With the development of semiconductor device manufacturing technology, the speed and integration of semiconductor devices have been improved. In addition, there has been an increasing need for small, high-density graphics. Wide isolation regions in semiconductor devices also require small high-density patterns. [0003] An oxide layer of Local Oxidation of Silicon (LOCOS) has been mainly used as the isolation layer of conventional semiconductor devices. However, the bird's beak structure is formed at the edge of the isolation layer by the LOCOS method, which reduces the area of ​​the active region and causes leakage current. [0004] Currently, a shallow trench isolation (STI) layer ha...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/76H01L21/762H10B12/00H10B99/00
CPCH01L27/1052H01L21/8239H01L21/76229H01L21/76H10B12/00
Inventor 朴柱昱
Owner SAMSUNG ELECTRONICS CO LTD
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