Semiconductor structure and forming method thereof

Abstract

The embodiment of the invention provides a semiconductor structure and a forming method thereof, and the method comprises the steps: providing a substrate and an insulating layer which are stacked, and enabling the interior of the substrate to be provided with a plurality of storage node contact structures at intervals; a latticed upper electrode layer is formed on the surface of the insulating layer, a plurality of meshes penetrating through the upper electrode layer are formed in the upper electrode layer, and the orthographic projection of each mesh on the insulating layer and the orthographic projection of one storage node contact structure on the insulating layer have an overlapping area; forming a dielectric layer on the side wall of the mesh; removing the insulating layer exposed from the meshes to expose the storage node contact structure; lower electrode layers are formed in the meshes, the lower electrode layers are located on the side, away from the upper electrode layer, of the dielectric layer and make contact with the exposed storage node contact structure, and the lower electrode layers in the different meshes are electrically insulated from one another. According to the semiconductor structure forming method provided by the embodiment of the invention, the area of the capacitor electrode plate of the semiconductor structure can be increased.

Description

technical field [0001] Embodiments of the present invention relate to the field of semiconductors, and in particular, to a semiconductor structure and a method for forming the same. Background technique [0002] Dynamic random access memory (Dynamic Random Access Memory, DRAM) is a semiconductor memory device commonly used in computers, which is composed of many repeated memory cells. Each memory cell includes a capacitor and a transistor. A large enough capacitance is the basic requirement to ensure the normal operation of the DRAM and sufficient storage retention time. In the DRAM process, the DRAM adopts a stacked capacitor structure. At present, the capacitor of the DRAM cell adopts The first is a hexagonal honeycomb layout, and the capacitors are cylindrical or columnar structures with extremely large aspect ratios. [0003] The current capacitor layout structure results in the word line to bit line pitch ratio being fixed at Left and right, the fixed word bit line p...

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Problems solved by technology

[0004] The embodiment of the present invention provides a semiconductor structure and its forming method, which solves the problem of insufficient area of ​​the capacitor electrode plate of the semiconductor structure

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