Neural network acceleration device and method and communication equipment

Abstract

The invention provides a neural network acceleration device and method and communication equipment, and belongs to the field of data processing, and the method specifically comprises the steps that a main memory receives and stores feature map data and weight data of a to-be-processed image; a main controller generates configuration information and an operation instruction according to the structure parameters of the neural network; a data caching module comprises a feature data caching unit for caching feature line data extracted from the feature map data and a convolution kernel caching unit for caching convolution kernel data extracted from the weight data; a data controller adjusts a data path according to the configuration information and the instruction information and controls the data flow extracted by a data extractor to be loaded to a corresponding neural network calculation unit, the neural network calculation unit at least completes convolution operation of one convolution kernel and feature map data and completes accumulation of multiple convolution results in at least one period, and therefore, circuit reconstruction and data multiplexing are realized; and an accumulator accumulates the convolution results and outputs output feature map data corresponding to a convolution core.

Description

technical field [0001] The invention relates to the field of data processing, in particular to a neural network acceleration device, method and communication equipment. Background technique [0002] A convolutional neural network consists of an input layer (input layer), any number of hidden layers (hidden layers) as intermediate layers, and an output layer (output layer). The input layer (inputlayer) has multiple input nodes (neurons). The output layer has output nodes (neurons) that recognize the number of objects. [0003] The convolution kernel is a small window set in the hidden layer, which holds the weight parameters. The convolution kernel slides sequentially on the input image according to the step size, and performs multiplication and addition operations with the input feature image of the corresponding area, that is, the weight parameter in the convolution kernel and the value of the corresponding input image are first multiplied and then summed. The traditiona...

AI Technical Summary

Problems solved by technology

The traditional convolution acceleration operation device needs to use the img2col method to expand the input feature map data and convolution kernel data in matrix form according to the convolution kernel size and step size parameters, and then perform operations on the expanded matrix, so that it can be calculated according to the matrix The multiplication operation rule performs convolution acceleration, but this method requires a larger on-chip cache after the feature data matrix is ​​expanded, and similarly requires more off-chip main memory reading frequency and cannot efficiently multiplex the read data. It needs to occupy the read and write bandwidth of the off-chip memory and increase the hardware power consumption. At the same time, the convolution acceleration method based on the img2col expansion method is not conducive to the hardware logic circuit implementation of the convolution operation of different sizes of convolution kernels and step sizes. Therefore, In the process of convolution network operation, each input channel needs to perform convolution matrix operation with multiple convolution kernels, and the feature map data needs to be acquired multiple times; and all feature map data on each channel are all cached in the buffer , the amount of data is not only huge, but also when the convolution matrix is ​​calculated, since the size of the feature data after matrix conversion is far greater than the size of the original feature data, not only will the on-chip storage resources be wasted, so it is impossible to perform large-scale operations

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