Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

A Block Matrix Storage Method in Circuit Simulation

A block-matrix and circuit simulation technology, applied in electrical digital data processing, instruments, complex mathematical operations, etc., can solve problems such as excessive data volume, slow speed, and difficulty in parallel processing, achieving accelerated calculation and reduced requirements , the effect of improving computing efficiency

Active Publication Date: 2022-05-24
成都华大九天科技有限公司
View PDF5 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

First of all, when the size of matrix A increases, the amount of data in A itself increases, and it is necessary to read and write vectors equal to the dimension in the calculation, and the scale will also increase, causing the amount of data to exceed the cache of the computer CPU, resulting in slow down
Secondly, it is difficult to do parallel processing directly on the calculation of A matrix, and the parallel ability of modern computers cannot be effectively used

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • A Block Matrix Storage Method in Circuit Simulation
  • A Block Matrix Storage Method in Circuit Simulation
  • A Block Matrix Storage Method in Circuit Simulation

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0033] Figure 1 For a flowchart of a block matrix storage method in circuit simulation of the present invention, reference will be made below Figure 1 , a detailed description of the block matrix storage method in circuit simulation of the present invention.

[0034] First, in step 101, the circuit nodes are renumbered according to the circuit division, a new sub-matrix is established.

[0035] In an embodiment of the present invention, the nodes of each subcircuit are renumbered according to the rules of the internal node in front and the boundary node in the back.

[0036] In an embodiment of the present invention, all nodes are renumbered in the order of traversing the internal nodes of each subcircuit, and then traversing the boundary nodes.

[0037] Each subcircuit builds a new sub-matrix using the connected nodes according to the relative order of the renumbered nodes.

[0038] In step 102, iterates through all the devices, according to the node number of the subcircuit and p...

Embodiment 2

[0051] The following in conjunction with a specific embodiment of the circuit simulation of the present invention in the block matrix storage method is further described.

[0052] Figure 2 For a circuit diagram according to one embodiment of the present invention, using the block matrix storage method of the present invention, pair Figure 2 The circuit in the implementation of the calculation, which can be performed as follows:

[0053] Suppose node 2 and node 4 are boundary nodes; nodes 1, V1, G1, G2, and C2 belong to the first subcircuit, and nodes 3, C1, and I1 belong to the second subcircuit.

[0054] In step 1, the circuit nodes are renumbered by circuit division, following the rules of internal nodes first and boundary nodes behind. Each subcircuit numbers the connected nodes in this order, resulting in Figure 3 The numbered table in .

[0055] In step 2, iterate over all the devices, each adding coefficients to the matrix to which it belongs. get Figure 4 ， Figure 5 2 subm...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

A block matrix storage method in circuit simulation, comprising the following steps: renumbering and sorting the nodes of each sub-circuit to establish a sub-matrix of nodes; The non-zero element position is marked in the corresponding sub-matrix; the Schur complement matrix of each sub-matrix is ​​calculated and merged to generate the top-level matrix. The block matrix storage method in the circuit simulation of the present invention divides the coefficient matrix of the circuit equation system into blocks, so that the subsequent matrix calculation, including matrix decomposition and back-substitution solution, can be performed in parallel, and the calculation efficiency is improved.

Description

Technical field [0001] The present invention relates to the field of numerical simulation technology for analog circuits, in particular to a block matrix storage method for dividing the circuit into a later range group coefficient matrix. Background [0002] The current in the circuit follows Kirchhoff's law of currents (KCL equation), and the sum of the total currents of all branches connected by any node is zero. In the system of linear equations Ax=y calculated by circuit simulation, the coefficient matrix A reflects the effect of the state variable x on the result y (mainly the node current and). The dimensionality of A is basically the same as the number of nodes in the circuit, and as the size of the simulated circuit increases, the A matrix also increases. In the matrix storage and calculation of circuit simulation, the A matrix is currently stored directly as a matrix, and there are many defects. First of all, when the scale of the A matrix increases, the amount of data i...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Patents(China)
IPC IPC(8): G06F30/367G06F17/16
CPCG06F30/367G06F17/16
Inventor 陶雄周振亚吴大可程明厚刘强
Owner 成都华大九天科技有限公司
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic, Popular Technical Reports.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap|About US| Contact US: help@patsnap.com