Multi-gate device and forming method thereof

Abstract

The invention relates to a multi-gate device and a method of forming the same. An exemplary device includes a channel layer, a first epitaxial source / drain feature, and a second epitaxial source / drain feature disposed over a substrate. The channel layer is disposed between the first epitaxial source / drain feature and the second epitaxial source / drain feature. A metal gate is disposed between the first epitaxial source / drain feature and the second epitaxial source / drain feature. The metal gate is disposed over and in physical contact with at least two sides of the channel layer. A source / drain contact is disposed over the first epitaxial source / drain feature. A doped crystalline semiconductor layer, such as a gallium doped crystalline germanium layer, is disposed between the first epitaxial source / drain feature and the source / drain contact. The doped crystalline semiconductor layer is disposed over and in physical contact with at least two sides of the first epitaxial source / drain feature. In some embodiments, the doped crystalline semiconductor layer has a contact resistivity of less than about 1 * 10 <-9 > [Omega]-cm < 2 >.

Description

technical field [0001] Embodiments of the present application relate to multi-gate devices and methods of forming the same. Background technique [0002] Multi-gate devices have been introduced to meet the growing demands of the integrated circuit (IC) industry for ever smaller and faster electronic devices that can simultaneously support an increasing number of increasingly complex and sophisticated Function. A multi-gate device has a gate extending partially or fully around a channel region to provide access to the channel region on at least two sides. Exemplary multi-gate devices include Fin Field Effect (FinFET) transistors, Gate All-Around (GAA) transistors (e.g., nanowire-based transistors), and / or other three-dimensional (3D) transistors, all of which may be referred to as non-planar transistor. Multi-gate devices enable massive scaling of IC technology and have been observed to improve gate control, increase gate-channel coupling, reduce off-state current, and / or ...

AI Technical Summary

Problems solved by technology

However, current contact resistivity reduction methods are not compatible with the fabrication of non-planar transistors

Thus, while existing source / drain contact structures for multi-gate devices and methods for fabricating them have generally been adequate for their intended purposes, they have not been entirely satisfactory in all respects. Satisfied

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