Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

Preparation method of source and drain electrodes of high-electron-mobility transistor

A high electron mobility, source-drain electrode technology, applied in the direction of circuits, electrical components, semiconductor devices, etc., to reduce costs, reduce error requirements, and improve performance

Active Publication Date: 2021-04-20
FUDAN UNIV
View PDF13 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] The purpose of the present invention is to provide a method for preparing the source and drain electrodes of high electron mobility transistors with low manufacturing cost and simple process, so as to solve the problem of accurately controlling the distance between the source and drain electrodes and the gate during the preparation process of high electron mobility transistors problem, for higher device performance

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Preparation method of source and drain electrodes of high-electron-mobility transistor
  • Preparation method of source and drain electrodes of high-electron-mobility transistor
  • Preparation method of source and drain electrodes of high-electron-mobility transistor

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0046] Example 1: Preparation of InP-based high electron mobility transistor source and drain electrodes by corner evaporation self-alignment process

[0047] (1) Select a T-shaped gate with a gate width of 30nm, a gate height of 150nm, a gate width of 500nm, a height of 200nm, and an InP-based high electron mobility transistor substrate with a gate groove corrosion depth of 20nm. Such as Figure 8 shown;

[0048](2) Spin-coat the LOR sacrificial layer on the substrate at a speed of 4000 RPM, and bake it in an oven at 180°C for 30 minutes to cure and take it out, such as Figure 9 shown;

[0049] (3) Continue to spin-coat AZ5214 photoresist on the substrate at a speed of 4000RPM, and bake it on a hot plate at 95°C for 90 seconds to cure. The result is as follows: Figure 10 shown;

[0050] (4) The sample is subjected to an overlay exposure treatment of 6.25mW / cm in a contact optical lithography machine 2 The power exposure is 6.7s. The result is as Figure 11 shown;

...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

PropertyMeasurementUnit
heightaaaaaaaaaa
widthaaaaaaaaaa
depthaaaaaaaaaa
Login to View More

Abstract

The invention belongs to the technical field of transistor preparation, and particularly relates to a preparation method of source and drain electrodes of a high-electron-mobility transistor. The preparation method provided by the invention adopts an angular evaporation self-alignment process, and basically comprises the following steps: on the basis of a T-shaped gate growth process, accurately controlling the distance between a source electrode and a gate electrode and the distance between a drain electrode and the gate electrode of a high-electron-mobility transistor device in an angular evaporation manner by utilizing a unique T-shaped structure of the gate electrode of the high-electron-mobility transistor; therefore, the positions of the source electrode, the drain electrode and the T-shaped gate of the high-electron-mobility transistor device achieve the purpose of position-controllable self-alignment, and finally, a new adjustable geometrical parameter freedom degree is provided for improving the performance of the device. The method provided by the invention can be used for preparing a high-electron-mobility transistor device with a T-shaped gate structure to obtain a symmetrical or asymmetrical distance between a source and a gate and a distance between a drain and the gate, and is compatible with the existing semiconductor process at the same time.

Description

technical field [0001] The invention belongs to the technical field of transistor preparation, and in particular relates to a method for preparing source and drain electrodes of high electron mobility transistors. Background technique [0002] As the field of wireless communication develops towards higher speed and lower latency. High electron mobility transistors with higher electron mobility will be more widely used in the communication market due to their higher frequency and lower communication delay. However, because high electron mobility transistors obtain higher cut-off frequency characteristics, higher processing precision must be required, which greatly increases the cost of high electron mobility transistor devices and limits its large-scale application. Generally speaking, in order to obtain higher frequencies, in addition to optimizing the layered structure of materials, appropriately reducing the drain-to-gate spacing can increase the maximum available gain of...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/28H01L29/40H01L29/417H01L29/778
Inventor 陈宜方祝鸣赛
Owner FUDAN UNIV
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products