Delay line calibration circuit for FPGA type time-to-digital converter

Abstract

The invention discloses a delay line calibration circuit for an FPGA type time-to-digital converter. The delay line calibration circuit is composed of a ring oscillator circuit, a control circuit anda CAL_RAM and LUT_RAM storage unit; the ring oscillator circuit is controlled by a reset signal to start oscillation and is used for generating a random pulse signal for calibration; the control circuit controls reading and writing of a CAL_RAM and a LUT_RAM through a finite-state machine, and completes the calibration of a delay line and accumulation of count values; a CAL_RAM and LUT_RAM circuitis realized by calling a Block RAM IP core; in a calibration state, the CAL_RAM is used for storing the frequency of hopping at each delay unit in the delay line; and in the accumulation state, the LUT_RAM is used for storing the accumulated value of the hopping times. The calibration circuit provided by the invention is good in transportability, can quickly perform online calibration on the delay line, reduces the influence of temperature / voltage on delay of the delay line, and improves the measurement precision of a TDC.

Description

technical field [0001] The invention relates to the field of integrated circuit measurement, in particular to a delay line calibration circuit for an FPGA type time-to-digital converter. Background technique [0002] High-precision time interval measurement technology has a wide range of applications not only in theoretical research fields such as molecular biology, nuclear physics detection and astronomical observation, but also in engineering practice fields such as laser ranging, high-precision positioning and food and drug safety monitoring. The construction of economy and national defense industry is of great significance. [0003] Time-to-digital conversion (TDC) technology is an important means of high-precision time interval measurement. It can directly convert the time quantity into a digital quantity, and has the advantages of high precision and strong anti-interference ability. Most industrial-grade time-to-digital converters are primarily implemented using appli...

AI Technical Summary

Problems solved by technology

In order to reduce the impact of temperature / voltage changes on TDC measurement accuracy, literature [2] proposed a Wave Union method for delay line calibration circuits to perform online calibration of delay lines, but in the implementation of this method, FPGA was used The external crystal oscillator provides the random signal required for calibration, resulting in poor portability of the calibration circuit; literature [3] based on statistical principles, designed a pipelined online calibration circuit using a dual-phase delay line

Although this circuit effectively improves the calibration accuracy, it requires a large first-in-first-out (FIFO) storage depth to meet the calibration times, which limits the improvement of calibration accuracy to a certain extent.

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