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Method for realizing excitation and inhibition functions of synapses

A synaptic and exciting technology, applied in the synaptic field of neuromorphic computing, can solve problems such as changes in device channel conductance, and achieve the effect of plasticity and maintaining characteristics

Active Publication Date: 2021-02-19
PEKING UNIV
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Problems solved by technology

At this time, the non-volatile spontaneous polarization of the ferroelectric material will induce additional charges on the gate oxide layer of the MOSFET, resulting in a change in the device channel conductance

Method used

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  • Method for realizing excitation and inhibition functions of synapses

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Embodiment Construction

[0015] The present invention will be further elaborated below through specific embodiments in conjunction with the accompanying drawings.

[0016] This embodiment uses Hf 0.5 Zr 0.5 o 2 The ferroelectric transistor FeFET of ferroelectric material, at this time, the spontaneous polarization of ferroelectric material will induce additional charges on the gate oxide layer of PMOS, resulting in a change in the channel conductance of the device. The charge induced by the ferroelectric polarization charge on the PMOS gate oxide layer can also be equivalent to an additional gate voltage, which can be reflected on the entire FeFET as a change in the channel conductance of the device.

[0017] Such as figure 1 As shown, the present embodiment is based on ferroelectric transistors with excitatory and inhibitory synaptic circuits, including ferroelectric transistors FeFET and PMOS; wherein, FeFET is used to realize the plasticity and retention characteristics of synapses, programming ...

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Abstract

The invention provides a method for realizing excitation and inhibition functions of synapses, and belongs to the technical field of synapse hardware in neuromorphic calculation. According to the method, a ferroelectric transistor FeFET and a PMOS are adopted to form a synapse circuit; the FeFET realizes the plasticity and memory characteristics of synapses, the gate end of the FeFET is used as aprogramming (or erasing) port, the source end of the FeFET is biased as suppression voltage, and the drain end of the FeFET is connected to the drain end of the PMOS and used as a synapse voltage output end; the source end of the PMOS is used as the pulse input end of a preceding-stage neuron, and the gate end of the PMOS is biased at a fixed power supply voltage; when the front-stage neuron transmits voltage output, the PMOS channel resistor and the FeFET channel resistor divide the voltage to generate synaptic excitation type or suppression type voltage output. Compared with a traditional MOSFET-based implementation mode, the method has the advantages that the hardware overhead can be remarkably reduced, the driving capacity is high, and large-scale high-interconnection neural network hardware implementation is facilitated.

Description

technical field [0001] The invention belongs to the technical field of synapses in neuromorphic computing, and in particular relates to a method for realizing synapses with excitatory and inhibitory functions based on ferroelectric transistors. Background technique [0002] With the vigorous development of information technology, human society has entered the era of "data explosion", and the annual exponential growth of data volume has brought unprecedented pressure on data processing and calculation. Due to the characteristics of the traditional von Neumann computing architecture, which separates storage and computing, the transmission of data between the storage unit and the computing unit will cause a lot of waste of power consumption and energy consumption. In today's information society and even the intelligent society, there is a huge amount of data In this context, this problem will become more and more serious. [0003] Inspired by the computing model of the human b...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06N3/063
CPCG06N3/063Y02D10/00
Inventor 黄如罗金刘天翊黄芊芊
Owner PEKING UNIV
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