Two-bit memory cell and its circuit structure for in-memory computing

Abstract

A double-bit storage unit structure and its array structure and circuit structure in an in-memory computing chip. The double-bit storage unit includes three transistors, and the three transistors are connected in series, a selection transistor is used as a switch in the middle, and two charge storage transistors are arranged symmetrically on both sides. The storage array composed of the double-bit storage unit is used to store the weight of the neural network, and the multiplication and accumulation operation of the neural network is performed through a two-step current detection method. The invention can effectively control leakage current, realize higher weight storage density and stronger reliability, and further realize neural network operation with more practical significance.

Description

technical field [0001] The invention relates to the field of memory unit and in-memory computing chip circuit design, in particular to a double-bit memory unit structure, a memory array architecture based on the double-bit memory unit structure, and a circuit architecture applied in the field of in-memory computing. Background technique [0002] Deep neural network is one of the perception models with the highest level of development in the field of artificial intelligence. It simulates the neural connection structure of the human brain by establishing a model, and describes the data characteristics hierarchically through multiple transformation stages, providing images, videos, audios, etc. Large-scale data processing tasks bring breakthrough progress. A deep neural network model is a computational model that consists of a large number of nodes connected through a mesh structure, and these nodes are called neurons. The connection strength between every two nodes is express...

AI Technical Summary

Problems solved by technology

[0007] Existing in-memory computing circuits based on SONOS or Floating Gate technology use transistors to bind charge storage weights, but their storage cell technology has serious reliability problems after the weight order is too high or the number of weight erasures increases, which is manifested as erasure. Phenomena such as interference and leakage current generated by over erase affect the power consumption, operation accuracy and reliability of the neural network system

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