Packaging structure, semiconductor device and packaging method

Abstract

The invention discloses a packaging structure, a semiconductor device and a packaging method. The packaging structure comprises a chip unit which comprises a substrate and a client layer located on the surface of the substrate, wherein the surface, deviating from the substrate, of the client layer is defined as a first surface, the surface, deviating from the client layer, of the substrate is defined as a second surface, and a welding pad is formed in the client layer; welding bulges which are formed on the second surfaces of the chip units; a metal wiring layer which is electrically connectedbetween the welding pad and the welding bulges; and an insulating layer which is formed between the metal wiring layer and the chip unit, wherein the insulating layer comprises a silicon dioxide layer and a Si3N4 layer which are sequentially formed on the surface of the chip unit. The insulating layer of the packaging structure adopts a SiO2 + Si3N4 + epoxy resin three-layer structure, and through the structure, the moisture isolation effect can be greatly improved, and the stress resistance strength of the packaging structure is also greatly improved.

Description

technical field [0001] The invention belongs to the technical field of semiconductors, and in particular relates to a packaging structure, a semiconductor device and a packaging method, and is particularly suitable for TSV (Through Silicon Via Technology) packaging of 40nm and below Low-k (low dielectric loss constant) chips. Background technique [0002] Wafer Level Chip Size Packaging (WLCSP) technology is a technology that performs packaging and testing on the entire wafer and then cuts it to obtain a single finished chip. The size of the packaged chip is the same as that of the bare chip. Wafer-level chip packaging technology subverts traditional packaging such as ceramic leadless chip carrier (Ceramic Leadless ChipCarrier), organic leadless chip carrier (Organic Leadless ChipCarrier), and conforms to the market's increasingly light, small and short microelectronic products. , Thinning and low price requirements. The chip packaged by the wafer-level chip packaging techn...

AI Technical Summary

Problems solved by technology

[0004] An embodiment of the present invention provides a packaging structure, a semiconductor device and a packaging method, which are used to solve the problems in the prior art that the welding pad itself is cracked or the adjacent customer layer is broken due to the large CTE of the insulating layer, including:

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