A carbon nanotube three-dimensional fin transistor and its preparation method

Abstract

The present application discloses a carbon nanotube three-dimensional fin transistor and a preparation method thereof, wherein the carbon nanotube three-dimensional fin transistor is a kind of Dirac two-dimensional semi-metal source and drain based on an embedded gate fin Transistor structure, the carbon nanotube three-dimensional fin transistor with this structure can reduce the short channel effect of the carbon nanotube three-dimensional fin transistor while having a small size, because the Dirac two-dimensional semi-metal has a two-dimensional The ultra-thin structure, using it as the source and drain materials of the carbon nanotube three-dimensional fin transistor can reduce the electrostatic shielding effect of the source and drain on the gate electrode in the gate structure, thereby reducing the short-circuit of the carbon nanotube three-dimensional fin transistor. channeling effect. In addition, the carbon nanotube three-dimensional fin transistor can affect the potential distribution in the channel by applying a voltage on the embedded metal gate fin, thereby realizing discrete adjustment and control of the device threshold and realizing the function of dynamically controlling the device threshold.

Description

technical field [0001] The present application relates to the field of semiconductor technology, and more specifically, relates to a carbon nanotube three-dimensional fin transistor and a preparation method thereof. Background technique [0002] Moore's Law means that when the price remains constant, the number of components that can be accommodated on an integrated circuit will double every 18-24 months, and the performance will also double. [0003] With the continuous shrinking of the size of semiconductor devices, it becomes more and more difficult for field effect transistors in traditional two-dimensional structure CMOS (Complementary Metal Oxide Semiconductor, Complementary Metal Oxide Semiconductor) integrated circuits to continue Moore's Law. And with the advancement of Moore's Law and the shrinking of the size of logic devices, the short-channel effect is becoming more and more obvious, such as the increase of the sub-threshold swing and the decrease of the potenti...

AI Technical Summary

Problems solved by technology

[0003] With the continuous shrinking of the size of semiconductor devices, it is becoming more and more difficult for field effect transistors in traditional two-dimensional structure CMOS (Complementary Metal Oxide Semiconductor, Complementary Metal Oxide Semiconductor) integrated circuits to continue Moore's Law

And with the advancement of Moore's law and the shrinking of the size of logic devices, the short-channel effect is becoming more and more obvious, such as the increase of sub-threshold swing and the decrease of the potential barrier caused by the drain, which all lead to the exponential off-state current of logic devices. level up

Images