Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

Neuromorphic calculation circuit based on multi-bit parallel binary synaptic array

A computing circuit and binary technology, applied in biological neural network models, electrical components, electrical signal transmission systems, etc., can solve the problems of low weight quantization accuracy and activation value quantization accuracy, deep neural network performance loss, unfavorable edge computing equipment applications, etc. problem, to achieve the effect of reducing power consumption and area, high precision and power consumption, and low power consumption

Active Publication Date: 2019-10-25
ZHEJIANG UNIV
View PDF5 Cites 11 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] Most of the currently proposed neuromorphic computing circuits require high-precision digital-to-analog converters (DACs, Digital-to-Analog Converters) and analog-to-digital converters (ADCs, Analog-to-Digital Converters) as interface devices, resulting in the Energy consumption accounts for more than 80% of the overall energy consumption, which is not conducive to the application in edge computing devices
Moreover, the current neuromorphic computing solution achieves low weight quantization accuracy and activation value quantization accuracy, and can only be used for simple networks such as Lenet. For large-scale deep neural networks such as Alexnet, the performance loss is obvious, which largely limits its performance. scope of application

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Neuromorphic calculation circuit based on multi-bit parallel binary synaptic array
  • Neuromorphic calculation circuit based on multi-bit parallel binary synaptic array
  • Neuromorphic calculation circuit based on multi-bit parallel binary synaptic array

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0019] The specific implementation manners of the present invention will be further described in detail below in conjunction with the accompanying drawings.

[0020] image 3 It is the neural synapse array structure adopted by the present invention. N binary RRAMs are used to simulate a synapse, so an N-bit fixed-point weight can be expressed as w=a n-1 a n-2 …a 0 , further the dendrite output can be expressed as:

[0021] y=∑x i w i =∑2 n-1 a i,n-1 x i +…+∑2 1 a i,1 x i +∑2 0 a i,0 x i (1)

[0022] Figure 5 and Figure 6 It is the specific calculation circuit integration principle and integration system. Each integrator consists of an integrating op amp, C n Capacitance, C f -C n Capacitor and S1, S2, S3, S4 switches, the specific connection relationship is shown in the figure. Using 256 parallel inputs, each input data is quantized into N-bit fixed points, and enters the integration circuit sequentially from low to high, in other words, A 0,0 A 1,0 …...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention discloses a neuromorphic calculation circuit based on a multi-bit parallel binary synapse array. The neuromorphic calculation circuit comprises a neural axon module, the multi-bit parallel binary RRAM synapse array, a time division multiplexer, a plurality of integrators and a shared successive approximation analog-to-digital converter, wherein the neural axon module comprises two basic units, namely a time sequence scheduler and an adder, and the time sequence scheduler is used for arranging the time sequence of signals, so that input signals are sequentially input into a multi-bit parallel binary RRAM synapse array by adopting a dendritic priority strategy; the adder is used for expanding the array scale, and when the configured neural network input layer is greater than the input of one RRAM array, the adder is used for adding the calculation results of the plurality of arrays to obtain the output of the network layer. Compared with the current system, the method has the advantages of high precision and low power consumption, can be configured into most deep neural network applications, and is particularly suitable for being deployed in edge computing equipment with high energy consumption requirements.

Description

technical field [0001] The invention belongs to the field of neuromorphic computing, and relates to a neuromorphic computing circuit based on a multi-bit parallel binary neural network synapse array. Background technique [0002] In recent years, deep neural networks have developed rapidly in the field of artificial intelligence, and have achieved excellent results in image recognition and natural language processing. At present, many advanced deep learning algorithms improve the performance of the network by increasing the depth of the network and the number of parameters, and put forward higher requirements for the storage capacity, computing power and energy efficiency of the hardware. For example, AlphaGo needs to consume one million watts of energy to obtain enough computing power, compared with the human brain which only needs to consume 20 watts of energy. [0003] Neuromorphic computing can greatly improve the energy efficiency of artificial neural network computing...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
IPC IPC(8): G06N3/063H03M1/46
CPCH03M1/468G06N3/065
Inventor 黄科杰张赛沈海斌
Owner ZHEJIANG UNIV
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products