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MOSFET and method for fabricating same

An n-type and p-type technology, applied in the field of device manufacturing, can solve the problems of large switching loss and large on-resistance, and achieve the effects of high applicable voltage, low power consumption, and low energy loss.

Inactive Publication Date: 2019-08-16
红与蓝微电子(上海)有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0008] The purpose of the present invention is to provide a MOSFET tube and its preparation method to solve the technical problems of large on-resistance and large switching loss of existing semiconductor field effect transistors.

Method used

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  • MOSFET and method for fabricating same
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  • MOSFET and method for fabricating same

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preparation example Construction

[0061] Another aspect of the present invention provides a method for preparing the above-mentioned MOSFET tube. combine Figure 1-3 , the preparation side of described MOSFET tube comprises the steps:

[0062] S01: along the direction extending outward from one surface of the substrate 1, the first n-type Si-doped GaN layer 22, the device drift layer 21, the p-type doped GaN layer 3, the second n-type Si-doped GaN layer 3, and the second Type Si-doped GaN layer 4; formed as figure 2 The layer structure shown.

[0063] S02: Etching the edges of the device drift layer 21, the p-type doped GaN layer 3, and the second n-type Si-doped GaN layer 4 to form image 3 The MESA structure shown;

[0064] S03: Etching the middle sections of the p-type doped GaN layer 3 and the second n-type Si-doped GaN layer 4 to form trenches, the trenches penetrating to the surface of the device drift layer 21;

[0065] S04: Depositing a growth gate insulating layer 5 on the inner wall of the tren...

Embodiment 1

[0079] This implementation provides a MOSFET tube, including:

[0080] GaN substrate;

[0081] Substrate, n+-type Si-doped GaN layer thickness 1 μm and lightly Si-doped n-type Si-doped GaN thickness 6 μm;

[0082] The thickness of the P-type Mg-doped GaN layer is 0.3 μm;

[0083] The thickness of the n+ type Si-doped GaN layer is 0.2 μm;

[0084] The thickness of the AlSiO gate insulating layer is 50nm;

[0085] Ti(15nm) / Au(125nm) metal gate;

[0086] Ti(10nm) / Al(240nm) source and Al(250nm) drain;

[0087] SOG field plate dielectric layer;

[0088] This embodiment also provides a preparation method for the MOSFET tube, including:

[0089] Using molecular beam epitaxy (MBE), sequentially grow n+-type Si-doped GaN layers, lightly Si-doped n-type Si-doped GaN layers, p-type Mg-doped GaN layers, n+-type Si-doped GaN layers, and n+-type Si-doped GaN layers on GaN substrates. GaN layer;

[0090] Subsequently, through Cl 2 / SiCl 4 Dry etching on the above layer structure to...

Embodiment 2

[0098] This implementation provides a MOSFET tube, including:

[0099] SiC substrate;

[0100] Substrate, n+-type Si-doped GaN layer thickness 0.4 μm and lightly Si-doped n-type Si-doped GaN thickness 3 μm;

[0101] The thickness of the P-type Mg-doped GaN layer is 0.1 μm;

[0102] The thickness of the n+ type Si-doped GaN layer is 0.1 μm;

[0103] The thickness of the Al2O3 gate insulating layer is 40nm;

[0104] Ti(15nm) / Au(125nm) metal gate;

[0105] Ti(10nm) / Al(240nm) source and Al(250nm) drain;

[0106] SOG field plate dielectric layer;

[0107] This embodiment also provides a preparation method for the MOSFET tube, including:

[0108] Using organic chemical vapor deposition (MOCVD) to sequentially grow n+-type Si-doped GaN layers, lightly Si-doped n-type Si-doped GaN layers, P-type Mg-doped GaN layers, n+-type Si-doped GaN layers, and n+-type Si-doped GaN layers on GaN substrates. Doped GaN layer;

[0109] Subsequently, through Cl 2 / SiCl 4 Dry etching on the a...

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Abstract

It is an object of the invention to provide a MOSFET and a method for fabricating the same. The novel GaN device structure provided by the invention combines a vertical trench structure with an AlSiOoxide, uses spin-on-glass (SOG) as a field plate dielectric and makes a contact hole to ingeniously form a field plate structure, thereby reducing the maximum electric field of an oxide, achieving lowpower loss, high device breakdown voltage, reducing effective on-resistance, and achieving good thermal conductivity.

Description

technical field [0001] The invention belongs to the field of device manufacturing in semiconductor technology, and in particular relates to a MOSFET tube and a preparation method thereof. Background technique [0002] In the development of power electronics industry, semiconductor technology has played a decisive role, among which power semiconductor devices have always been considered as a key component of power electronics equipment. Semiconductor field effect transistors have been highly valued and studied deeply at home and abroad recently. High-current switching devices require high reverse breakdown voltage and low on-resistance, large breakdown electric field, high electron drift rate, high electron mobility and high thermal conductivity, making Gallium Nitride (GaN) a popular choice for power device manufacturing. an attractive candidate material. Compared with silicon metal-oxide-semiconductor field-effect transistors of the same power level, gallium nitride (GaN)...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L29/78H01L29/20H01L29/40H01L21/336
CPCH01L29/7811H01L29/7813H01L29/2003H01L29/405H01L29/66734
Inventor 刘新科陈勇王佳乐胡聪邓煊华吴健华贺威
Owner 红与蓝微电子(上海)有限公司
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