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Multi-thread deterministic execution method based on weak memory consistency

An execution method and a deterministic technology, applied in the field of multi-threaded deterministic execution based on weak memory consistency, can solve the problem of paying a lot of extra overhead, and achieve the effects of improving performance, ensuring determinism, and increasing parallelism

Active Publication Date: 2019-08-02
HARBIN INST OF TECH
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AI Technical Summary

Problems solved by technology

The core of deterministic execution technology is to control the synchronization, competition and interference between parallel executives, so that the executives can interact according to certain rules and order, so as to ensure that each execution can follow this rule and order, so that the program Even if executed in different environments, the same result can be obtained, but in order to obtain determinism, the system needs to pay a lot of additional overhead, so how to improve the performance of deterministic systems has become a current research hotspot

Method used

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  • Multi-thread deterministic execution method based on weak memory consistency
  • Multi-thread deterministic execution method based on weak memory consistency
  • Multi-thread deterministic execution method based on weak memory consistency

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Embodiment

[0015] refer to figure 2 , At the beginning, it is judged whether the synchronization operation is nested. If there is nesting, it needs to wait for all other threads to end before entering strict serial execution; otherwise, enter the normal execution process. In the normal execution process, the thread is put into the waiting queue of the corresponding relevant thread group, and then waits for the token. After obtaining the token, the memory is submitted and the original synchronization operation is performed. At this time, if the thread is the last thread in the waiting queue of the relevant thread group, the shared memory of the thread group is additionally submitted to the global shared memory. Finally all threads need to wait for the end of the entire serial phase.

[0016] refer to image 3 , first check the threads in the Bypass queue in turn, and decrement the value of the Bypass countdown counter by one. Then check whether its Bypass countdown counter is zero. If...

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Abstract

The invention provides a multi-thread deterministic execution method based on weak memory consistency. A weak memory consistency model, a serial stage thread parallelization module and a performance guidance marking module are included. According to the method, a TSO weak memory consistency concept is used, and a two-point innovative technology is provided and comprises a serial phase part threadparallelization technology and a performance guidance marking technology for helping a long parallel distance thread to skip a synchronization point. According to the method, the problem of performance reduction caused by global synchronization of an existing deterministic method can be solved, the problem of load imbalance of parallel stages is effectively solved by enabling some threads with longer parallel stages to skip specified synchronization points, and the performance of the deterministic technology is greatly improved.

Description

technical field [0001] The invention is applied to enhance the parallelism of the deterministic system and improve the performance of the deterministic system in a multi-thread environment. Background technique [0002] As we all know, in recent years, the growth law of chip performance defined by Moore's Law has gradually encountered bottlenecks, and the integration of chips has gradually been limited by physical laws. The increase in chip frequency has brought serious energy consumption and heat dissipation problems. The practice of parallel computing and on-chip multi-core processor (CMP, Chip Multiprocessor) is to integrate two or more processor cores on the same chip. urgent need for improvement. Different from traditional single-core processors, in multi-core processors, multiple tasks are executed simultaneously on multiple processor cores, and they share the bus and part of the cache, thereby increasing the overall processing capability and operating efficiency of t...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F9/48G06F9/52
CPCG06F9/4881G06F9/522Y02D10/00
Inventor 王开宇季振洲周一豪吴倩倩张源悍
Owner HARBIN INST OF TECH
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