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Edge computing hardware architecture based on RISC-V

A RISC-V, edge computing technology, applied in the computer field, can solve the problems of high power consumption, high cost, consumption, etc., and achieve the effect of low power consumption

Active Publication Date: 2019-07-12
SUN YAT SEN UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] 1. High cost: Currently, mainstream processor chips in the market are expensive. If the edge device performs artificial intelligence processing and then introduces GPU, the cost will be very expensive.
[0006] 2. Large area and high power consumption: Due to the application scenarios of edge devices, edge devices have high requirements for low power consumption and small area performance
The existing processor needs to take into account the previous version, and because of the instruction set used, compared with the processor designed with the same performance RISC-V instruction set, it needs to consume more logic circuits
This in turn comes at a higher cost in terms of power consumption and area
[0007] 3. On the mobile edge device side, traditional MCUs and embedded CPUs cannot complete artificial intelligence applications due to their on-chip storage and peripheral limitations.

Method used

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Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0047] Such as figure 1 As shown, a RISC-V-based edge computing hardware architecture 100 includes: a processor 110 based on the RISC-V instruction set, a communication protocol interface 120 connected to the processor 110 based on the RISC-V instruction set, and a communication protocol interface 120 connected CNN hardware accelerator 130 .

[0048] The processor 110 based on the RISC-V instruction set can be used to process and execute instructions compiled from high-level languages. If there is a need to operate and control the CNN hardware accelerator in the instructions, it will pass the communication protocol interface in the form of memory access 120 controls and operates the CNN hardware accelerator 130 .

[0049]The communication protocol interface 120 can be used to realize the communication between the processor 110 based on the RISC-V instruction set and the CNN hardware accelerator 130. The communication protocol has two data channels, one is the communication be...

Embodiment 2

[0052] Such as figure 2 As shown, a processor 110 based on the RISC-V instruction set includes an instruction fetch module 111 , an execution module 112 , a memory access module 113 , a data memory module 114 , and a peripheral communication module 115 .

[0053] The instruction fetching module 111 can be used to obtain instructions, determine whether branch prediction is required for the instruction, generate the address of the next instruction, and transmit the instruction value, address, prediction and other information to the execution module 112 .

[0054] The instruction fetch module 111 includes an instruction fetch module 1111 , an instruction fetch control module 1112 , and an instruction memory 1113 .

[0055] The instruction fetch module 1111 can be used to generate the instruction address, partially decode the instruction value sent back from the instruction fetch control module 1112, and decode whether it is a jump instruction. For the jump instruction, branch pr...

Embodiment 3

[0058] Such as figure 2 As shown, the execution module 112 in this embodiment further includes a decoding module 1121 , an instruction dispatching module 1122 , and a long instruction dependency module 1123 .

[0059] Among them, the decoding module 1121 is connected with the instruction fetching module 1111, and can be used to receive the instruction information from the instruction fetching module 1111, decode the instruction information, and decide whether to fetch the corresponding instruction from the register according to the decoding result. value. At the same time, the result information decoded by this instruction is transmitted to the instruction dispatch module 1122, and the instruction dispatch module 1122 decides to dispatch the information to the operation unit module 1124 for execution. The instruction dispatch module 1122 can be used to analyze the decoding information transmitted by the decoding module 1121 to decide whether to dispatch. The instruction dis...

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Abstract

The invention discloses an edge computing hardware architecture based on RISC-V. The edge computing hardware architecture comprises an edge computing controller based on an RISC-V instruction set, used for controlling a CNN hardware accelerator and processing the operation result of the CNN hardware accelerator; a communication protocol interface, realizing data communication between a RISC-V-based controller and a CNN hardware accelerator; and a CNN hardware accelerator used for carrying out convolution processing on the data in the specified memory and sending a result obtained after operation of the CNN accelerator to the controller. With the help of characteristics of free opening, concise and modular of the RISC-V instruction set, the edge computing hardware architecture solves problem of high requirements on low power consumption, low area and low cost of equipment on a edge computing end. Meanwhile, due to the fact that the RISC-V instruction set has independent expansibility and good backward compatibility, the processor designed on the basis of the RISC-V instruction set is applied to a mobile edge device end, and the problem that a traditional MCU cannot carry out lightweight artificial intelligence processing due to programming limitation can be solved.

Description

technical field [0001] The present invention relates to the field of computers, and more specifically, to a RISC-V-based edge computing hardware architecture. Background technique [0002] With the rapid development of the Internet, the application of the Internet of Things with the Internet as the core has also developed rapidly. A large number of IoT devices are distributed at the edge, and these edge devices generate a large amount of data every moment, and transmit this huge data to the cloud for processing. However, cloud data centers are usually difficult to process data from massive edge devices, and at the same time, it is difficult to meet the real-time requirements of the edge end, resulting in network congestion, high latency, and low quality of service for IoT devices. [0003] Edge computing is created to deal with the problems faced by traditional cloud computing in the application of edge devices. Edge computing provides services such as computing, storage, ...

Claims

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Application Information

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IPC IPC(8): G06F9/30G06N3/063G06N3/04
CPCG06F9/30003G06N3/063G06N3/045Y02D10/00
Inventor 谭洪舟廖普辉路崇何逸飞梁羽开魏新元谢舜道周永坤黎梓宏
Owner SUN YAT SEN UNIV
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