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Bi-directional ESD protection device

A device and contact area technology, applied in the field of electronic science and technology, can solve problems such as reducing robustness and increasing area, and achieve the effect of improving robustness and avoiding latch-up effect.

Active Publication Date: 2018-12-28
UNIV OF ELECTRONICS SCI & TECH OF CHINA
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

That is: the need for latch-free operation will reduce the robustness, and if the ESD robustness of the latch-free device needs to be improved, the area needs to be increased

Method used

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  • Bi-directional ESD protection device

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0030] like image 3 As shown, the device structure of this embodiment includes: P-type substrate 00, N-type epitaxy 01 located above the P-type substrate, NTOP layer 13 located above the N-type epitaxy; the first PWELL located on the left side above the N-type epitaxy region 201, the first N+ contact region 111 located above the interior of the first PWELL region, the first P+ contact region 211 located above the interior of the first PWELL region, and the first NTOP layer 121 located above the interior of the first PWELL region; wherein the first The P+ contact region 211 is located on the left side of the first N+ contact region 111, the first NTOP layer 121 is located on the right side of the first N+ contact region 111; the second PWELL region 202 located on the right side above the N-type epitaxy is located above the inside of the second PWELL region The second N+ contact region 112, the second P+ contact region 212 located above the interior of the second PWELL region, ...

Embodiment 2

[0032] like Figure 4 As shown, there is an NWELL area 10 between the first PWELL area 201 and the second PWELL area 202 , and the NTOP layer 13 is located above the inside of the NWELL area 10 .

[0033] This example works as follows:

[0034] When the anode ESD voltage rises, the device first breaks down at the PN junction formed by the second PWELL region 202 / NWELL region 10 on the surface. The hole current after breakdown flows through the second PWELL region 202 and the second P+ contact region 212 , and is drawn away by the metal cathode 32 . When the current flowing through the second P+ contact region 212 increases to a certain value, so that the voltage drop between the second PWELL 202 and the second N+ contact region 112 reaches 0.7V, the parasitic NPN transistor is turned on. The second N+ contact region 112 injects electrons into the second PWELL region, and most of the electrons pass through the second NTOP layer 122 and are collected by the NWELL region 10 . ...

Embodiment 3

[0040] like Figure 5 As shown, the main difference between this embodiment and Embodiment 2 is that a first N+ low trigger area 141 is provided between the first PWELL area 201 and the NWELL area 10, and a part of the first N+ low trigger area 141 is located in the first PWELL area 201, a part is located in the NWELL area 10; a second N+ low trigger area 142 is provided between the second PWELL area 202 and the NWELL area 10, and a part of the second N+ low trigger area 142 is in the second PWELL area 202, and a part is in the Within NWELL District 10.

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Abstract

A bi-directional ESD protection device comprises a P-type substrate, an N-type epitaxial layer, an NTOP layer, a first PWELL zone, a first N + contact region, a first P + contact region, a first NTOPlayer, a second PWELL region, a second N + contact region, a second P + contact region and a second NTOP layer; the first N + contact region and the first P + contact region form a metal anode by metal short-circuiting, the second N + contact region and the second P+ contact region form a metal cathode by metal short-circuiting. As the NTOP layer is introduced above the N-type epitaxial layer to change the current distribution, the IV curve of the device presents the characteristic of multiple snapbacks, and the robustness of the device under the ESD pulse current is improved; to avoid devicelatch-up, the sustain current can be adjusted by adjusting the spacing between the NTOP layer and the first PWELL region and the second PWELL region.

Description

technical field [0001] The invention belongs to the field of electronic science and technology, and mainly relates to the electrostatic discharge (ElectroStatic Discharge, referred to as ESD) protection technology on the integrated circuit chip, specifically relates to a class of devices with low power consumption and strong latch-up resistance. ) capability, ESD protection devices for high-voltage integrated circuits. Background technique [0002] ESD stands for Electrostatic Discharge, which is a common phenomenon in nature. ESD exists in every corner of people's daily life. But it is such a common electrical phenomenon that is a fatal threat to sophisticated integrated circuits. However, for chips that have been packaged, each power supply / input / output pin becomes a channel for pulse currents such as human body model (HBM), machine model (MM), and human body metal model (HMM). Strong ESD pulses will not only cause hard failure of the chip, but also induce various effec...

Claims

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Application Information

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IPC IPC(8): H01L27/02
CPCH01L27/0296
Inventor 乔明肖家木齐钊何林蓉梁龙飞梁旦业张波
Owner UNIV OF ELECTRONICS SCI & TECH OF CHINA
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