Design Method of Heterogeneous Reconfigurable Graph Computing Accelerator System Based on FPGA
A design method and accelerator technology, applied in computer-aided design, CAD circuit design, calculation, etc., can solve the problems of inefficient software level, low effective calculation rate, and low off-chip bandwidth utilization, and achieve low power consumption and acceleration Effect of Graph Algorithms
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[0055] FPGA in the embodiment of the present invention refers to Field Programmable Gate Arrays (Field Programmable GateArrays), and the system designed in the present invention is a heterogeneous system based on PC-FPGA, wherein, the data path between PC and FPGA can adopt PCI-E bus protocol. The data path inside the FPGA on-chip accelerator is illustrated by using the AXI bus protocol as an example to illustrate the data path in the drawings of the embodiments of the present invention, but the present invention is not limited thereto.
[0056] figure 1 It is a flowchart of an FPGA-based graph computing accelerator design method 100 according to an embodiment of the present invention. The method 100 includes:
[0057] S110, load the driver program required by the hardware device module, select a suitable computing engine according to the graph data to be processed, if the third type of computing engine is selected, preprocess the graph data, and transmit the preprocessed gr...
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