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Network equipment in ptp domain and tod synchronization method

A network device and a technology between devices, applied in the field of network communication, can solve problems such as poor time synchronization effect, achieve shortened time, ensure performance and stability requirements, and improve the effect of timing synchronization ability

Active Publication Date: 2019-12-13
NEW H3C TECH CO LTD
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In this synchronization mode, each PHY chip needs to wait for the 1PPS clock signal to update TOD, resulting in poor time synchronization effect.

Method used

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  • Network equipment in ptp domain and tod synchronization method
  • Network equipment in ptp domain and tod synchronization method
  • Network equipment in ptp domain and tod synchronization method

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Embodiment Construction

[0019] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of them. implementation. Based on the implementation manners in the present disclosure, all other implementation manners obtained by those skilled in the art without creative efforts fall within the protection scope of the present disclosure.

[0020] Generally, a network to which the PTP protocol is applied is called a PTP domain. There may be multiple network devices in the PTP domain, including a master device and a slave device. Multiple network devices exchange information based on the PTP protocol. The reference time of the entire PTP domain is the optimal clock (Grandmaster Clock, GM), and the time of the o...

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Abstract

The invention provides a network device in a PTP domain, and a TOD synchronization method, and relates to the technical field of network communication. The device comprises a main controller, a programmable logic device and PHY chips, where the main controller is used for separately setting a clock deviation in registers of the obtaining a PHY chips when the clock deviation between master and slave devices is obtained, and setting a pulse width and delay time of the programmable logic device to trigger the programmable logic device to generate a time synchronization pulse signal; the programmable logic device is used for generating the time synchronization pulse signal under the trigger of the main controller and separately sending the time synchronization pulse signal to the PHY chips; and the PHY chip is used for receiving the clock deviation for TOD synchronization after receiving the time synchronization pulse signal. by adoption of the network device in PTP domain, and TOD synchronization method provided by the invention, the time synchronization efficiency of the PHY chips is improved, thereby ensuring the time synchronization performance of the device in the PTP domain.

Description

technical field [0001] The present disclosure relates to the technical field of network communication, in particular to a network device in a PTP domain and a TOD synchronization method. Background technique [0002] In the process of network communication, the normal operation of many services requires clock synchronization, that is, the time or frequency difference between the entire network equipment is kept within a reasonable error level, such as PTP (Precision Time Protocol, high-precision time synchronization protocol) Under this mechanism, the time accuracy can reach sub-microseconds. Through the interaction of PTP protocol messages between the master and slave devices, the slave device can calculate the time offset (Offset) with the master device, thereby correcting the local time of the slave device. Complete time synchronization between master and slave devices. [0003] Usually, there are multiple PHY (Physical Layer) chips on the device, and each PHY chip has a...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H04J3/06
CPCH04J3/0667
Inventor 薛鸿飞肖冰
Owner NEW H3C TECH CO LTD
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